Why drain voltage of PA can go to 2Vdd but don't cause distortion?

I understand this above part. But it conflict with OP. In op, it said the output voltage cannot go beyond vdd，otherwise distortion will happen. Why here the drain can achieve 2Vdd?

Re: why drain voltage of PA can go to 2Vdd but don't cause distortion?

Coupling Capacitor acts as a Voltage source due to its high capacitance value.( its charge is constant as VDD ).Besides, the Inductor acts as a Constant Current Source due to its high inductance value.
Imagine that Current Source is open circuit for AC, Voltage Source short circuit for AC.Load Current also creates a swing around VDD so when you add or extract this sinusoidal swing you will see that the peak Load Voltage can reach 2*VDD.

The quescient voltage at the drain is VDD. Thus the drain voltage can go down ~1VDD voltage before M1 leaves the saturation region and would cause distortion.
In this direction the inductor is cahrging-up with extra energy, and when the drain voltage returns back to VDD the only way for the inductor to lose the extra energy is pulling-up the drain voltage above VDD, and lose the energy by a current through the capacitor and the resistor.
This amplitude has to be close to the 2VDD at the drain, because between the extra energy and the peak voltage (about -1VDD at the charging up of the inductor) there is connection.

frankrose said:

The quescient voltage at the drain is VDD. Thus the drain voltage can go down ~1VDD voltage before M1 leaves the saturation region and would cause distortion.
In this direction the inductor is cahrging-up with extra energy, and when the drain voltage returns back to VDD the only way for the inductor to lose the extra energy is pulling-up the drain voltage above VDD, and lose the energy by a current through the capacitor and the resistor.
This amplitude has to be close to the 2VDD at the drain, because between the extra energy and the peak voltage (about -1VDD at the charging up of the inductor) there is connection.

Click to expand...

BigBoss said:

Coupling Capacitor acts as a Voltage source due to its high capacitance value.( its charge is constant as VDD ).Besides, the Inductor acts as a Constant Current Source due to its high inductance value.
Imagine that Current Source is open circuit for AC, Voltage Source short circuit for AC.Load Current also creates a swing around VDD so when you add or extract this sinusoidal swing you will see that the peak Load Voltage can reach 2*VDD.

Click to expand...

Thanks!!! In OP design, we learn that Vout>Vdd can cause distortion. But why here it won't cause distortion when Vout=2Vdd? I think it already fit for the condition that Vout >Vdd.

If inductor is real, not ideal, the max voltage will be lower, and if you apply only resistor the max output voltage will be ~1VDD.
Vout can't be higher than a limit. Limit is 2VDD with ideal inductor, 1VDD with resistor.
I think in OP design you have learnt that with resistor the Vout can't be higher than Vdd, but with inductor it is not true. I think.

And distortion will be there always. There will be linear and non-linear distortion. Linear by the frequency-dependent devices, non-linear by the transistor.
There are 2 kinds of non-linear distortion:
- Soft: caused by the square-law characteristic of the transistor.
- Hard: appears when the input voltage amplitude is too high, and the output voltage "hits his head" into the supply rail or the transistor's Vds is lower than Vdsat under control.

So, when you say that "Vout>Vdd can cause distortion", I think it is not valid, Vout just can't be higher than Vdd (with resistor!), and if the input signal is too high that will cause hard distortion, but other kinds of distortions will be in the circuit next to lower amplitudes.