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  1. #1
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    Vivado HLS Experience

    Hi All,
    I'm interested in trying High-Level Synthesis, HLS. When reading Xilinx stuff about it it looks good, however...
    To me it looks more complicated than VHDL and verilog. I want to know if it is worth trying.

    What are your experience of HLS?
    In what type of projects or functions is it useful?

    Cheers

    •   Alt1st December 2017, 15:58

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  2. #2
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    Re: Vivado HLS Experience

    Hi. I dont have direct experience, but a few colleagues did.
    Overall conclusion was that it is good for quick prototyping and messing with simple designs, but the tools are less capable when going to more complex designs.
    It requires some good FPGA knowledge to get efficient results, and what the designers didnt like is that a lot of the design will change via menu options that are not obvious - so the same code can have 2 different implementation just from a check box - coming from people with HDL experience this made people uncomfortable.
    They also had to work around tool limitations at times. There were times when they were told things just couldnt be done with Vivado, but they found workarounds with slightly kludgy tcl scripts.

    So if you are comfortable with HDL, then you wont enjoy HLS initially. The main target market is programmers so they can sell them FPGAs.


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    •   Alt1st December 2017, 17:19

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  3. #3
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    Re: Vivado HLS Experience

    What are your experience of HLS?
    No experience.
    But our Xilinx FAE said that DSP benchmarks are now designed exclusively with HLS - No HDL.
    He said that with HLS there're able to get 70%-100% the performance compared to HDL.

    In what type of projects or functions is it useful?
    As far as I understand, it works well as long as the design has a single clock domain and mainly involves well defined structures that are replicated a lot. For example - Convolution ( basically a bunch of MAC operations).


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    •   Alt3rd December 2017, 07:48

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  4. #4
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    Re: Vivado HLS Experience

    Hello,

    I would like to ask one question related to porting C++ libraries using "Vivado HLS". I have encountered some dificulties when I was trying to port Arduino libray for small 1,3 inch OLED display. Here is the link for that OLED display:

    http://www.waveshare.com/1.3inch-oled-a.htm

    I would like to attach this display to my project based on Xilinx Spartan3 board (Elbert V2 board).

    I was looking for existing code (VHDL or Verilog) for this purpose, but it was unsuccessful.

    Then I decided to use "Vivado HLS" as solution for my problem. I have made few attempts to port simple general C++ libraries, and there were encouraging - generated code was readable and understandable. What was nice it also been generated in three languages: VHDL, SystemC and Verilog. After that I decide to try porting this Arduino library:

    http://github.com/adafruit/Adafruit_...it_SSD1306.cpp

    And after some time I stalled with this task. The reason is that this library is dependent on more specialized libraries that are depending on hardware (in this case AVR ATmega microcontroller). I mean te dependency of internal hardware details of AVR microcontrolerr like internal registers, timers and interrupts.

    And this is my question:

    How to implement hardware related parts during porting C++ libraries to HDL language using Vivado High Level Synthesis.

    So far I found some hints how to simulate interrupts:

    http://http://www.edaboard.com/thread6393.html

    http:///github.com/kevinpt/vhdl-extr...rrupt_ctl.vhdl

    , but the problem is more general (I also mean libraries from other hardware like STM32, ARM etc.)

    Coulkd I ask for some advices for my issues?

    Best regards



  5. #5
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    Re: Vivado HLS Experience

    Quote Originally Posted by FlyingDutch View Post
    I would like to attach this display to my project based on Xilinx Spartan3 board (Elbert V2 board).
    Because it migt be confusing, I would like to claryfing:

    My target device during attempts to port OLED Arduino library in "Vivado HLS" was Xilinx Artix-7 (exactly XC7A35T-1CPG236C from Digilent Cmod-A7 board)

    Regards



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