hareeshP
Member level 3
hi all,
I'm getting an error while doing RTL simulation on quartus, the comments are pasted below
Please anyone help me.
I'm getting an error while doing RTL simulation on quartus, the comments are pasted below
Code:
# Reading C:/intelFPGA/17.0/modelsim_ase/tcl/vsim/pref.tcl
# do po_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
# vmap work rtl_work
# Copying C:/intelFPGA/17.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
#
# vcom -87 -work work {C:/intelFPGA/17.0/signaltptutorial/po.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 19:34:43 on Nov 30,2017
# vcom -reportprogress 300 -87 -work work C:/intelFPGA/17.0/signaltptutorial/po.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity po
# -- Compiling architecture bhav of po
# End time: 19:34:43 on Nov 30,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# vcom -87 -work work {C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/testebecnh.vhd}
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 19:34:43 on Nov 30,2017
# vcom -reportprogress 300 -87 -work work C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/testebecnh.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity testebecnh
# -- Compiling architecture testebecnh_arch of testebecnh
# End time: 19:34:43 on Nov 30,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -voptargs="+acc" tb
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -voptargs=""+acc"" tb
# Start time: 19:34:44 on Nov 30,2017
# ** Error: (vsim-3170) Could not find 'tb'.
# Searched libraries:
# C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/altera
# C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/220model
# C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/sgate
# C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/altera_mf
# C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/altera_lnsim
# C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/fiftyfivenm
# C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/rtl_work
# C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/rtl_work
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./po_run_msim_rtl_vhdl.do PAUSED at line 12
Please anyone help me.
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