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  1. #1
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    modelsim error during RTL simulation

    hi all,

    I'm getting an error while doing RTL simulation on quartus, the comments are pasted below
    Code:
    # Reading C:/intelFPGA/17.0/modelsim_ase/tcl/vsim/pref.tcl
    # do po_run_msim_rtl_vhdl.do
    # if {[file exists rtl_work]} {
    # 	vdel -lib rtl_work -all
    # }
    # vlib rtl_work
    # vmap work rtl_work
    # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
    # vmap work rtl_work 
    # Copying C:/intelFPGA/17.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
    # Modifying modelsim.ini
    # 
    # vcom -87 -work work {C:/intelFPGA/17.0/signaltptutorial/po.vhd}
    # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
    # Start time: 19:34:43 on Nov 30,2017
    # vcom -reportprogress 300 -87 -work work C:/intelFPGA/17.0/signaltptutorial/po.vhd 
    # -- Loading package STANDARD
    # -- Loading package TEXTIO
    # -- Loading package std_logic_1164
    # -- Compiling entity po
    # -- Compiling architecture bhav of po
    # End time: 19:34:43 on Nov 30,2017, Elapsed time: 0:00:00
    # Errors: 0, Warnings: 0
    # 
    # vcom -87 -work work {C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/testebecnh.vhd}
    # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
    # Start time: 19:34:43 on Nov 30,2017
    # vcom -reportprogress 300 -87 -work work C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/testebecnh.vhd 
    # -- Loading package STANDARD
    # -- Loading package TEXTIO
    # -- Loading package std_logic_1164
    # -- Loading package std_logic_textio
    # -- Loading package std_logic_arith
    # -- Loading package STD_LOGIC_UNSIGNED
    # -- Compiling entity testebecnh
    # -- Compiling architecture testebecnh_arch of testebecnh
    # End time: 19:34:43 on Nov 30,2017, Elapsed time: 0:00:00
    # Errors: 0, Warnings: 0
    # 
    # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -voptargs="+acc"  tb
    # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -voptargs=""+acc"" tb 
    # Start time: 19:34:44 on Nov 30,2017
    # ** Error: (vsim-3170) Could not find 'tb'.
    #         Searched libraries:
    #             C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/altera
    #             C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/220model
    #             C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/sgate
    #             C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/altera_mf
    #             C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/altera_lnsim
    #             C:/intelFPGA/17.0/modelsim_ase/altera/vhdl/fiftyfivenm
    #             C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/rtl_work
    #             C:/intelFPGA/17.0/signaltptutorial/simulation/modelsim/rtl_work
    # Error loading design
    # Error: Error loading design
    #        Pausing macro execution
    # MACRO ./po_run_msim_rtl_vhdl.do PAUSED at line 12

    Please anyone help me.
    Last edited by ads-ee; 30th November 2017 at 16:42. Reason: added missing tags

  2. #2
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    Re: modelsim error during RTL simulation

    First tell us, what comes to your mind when you see the error message "** Error: (vsim-3170) Could not find 'tb'."

    Did you write this script yourself?

    Any please use "Code tags" when posting any type of code, be it RTL or some script (if I am not mistaken you are not posting for the 1st time in this forum).
    .....yes, I do this for fun!



    •   Alt30th November 2017, 15:51

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  3. #3
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    Re: modelsim error during RTL simulation

    As in the description, Modelsim could not find the tb module



    •   Alt30th November 2017, 16:03

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    Re: modelsim error during RTL simulation

    just open 'testebecnh.vhd' and see if you have a "tb" in there. my guess it is called something else. this is debugging 101, I am sure your class/instructor has covered this.
    Really, I am not Sam.



    •   Alt30th November 2017, 16:52

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    Re: modelsim error during RTL simulation

    Quote Originally Posted by ThisIsNotSam View Post
    just open 'testebecnh.vhd' and see if you have a "tb" in there. my guess it is called something else. this is debugging 101, I am sure your class/instructor has covered this.

    Hi,
    I am not able to debug the issue. what you mean by tb in testbecnh.vhd?



  6. #6
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    Re: modelsim error during RTL simulation

    You should read a vhdl tutorial then if you don't know what entity you have in your testbench file.
    Really, I am not Sam.



  7. #7
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    Re: modelsim error during RTL simulation

    Quote Originally Posted by ThisIsNotSam View Post
    You should read a vhdl tutorial then if you don't know what entity you have in your testbench file.
    I got the solution, the test bench entity name was incorrect in compile test bench.










    everyone was once a beginner....



  8. #8
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    Re: modelsim error during RTL simulation

    Quote Originally Posted by hareeshP View Post
    everyone was once a beginner....
    Sure. That being said, I still think you should read some vhdl / digital design material.
    Really, I am not Sam.



    •   Alt30th November 2017, 18:24

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  9. #9
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    Re: modelsim error during RTL simulation

    Quote Originally Posted by hareeshP View Post
    I got the solution, the test bench entity name was incorrect in compile test bench.
    probably, but testebecnh.vhd clearly exists as a file as otherwise there would have been an error.
    I guess the correct file actually has an entity called tb inside it. And testebecnh did not.



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