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    Implementation of output wrt clock in verilog

    I want to design module in which outputs are sequential and are displayed with the interval of count of the counter. for example: if count is from 1 to 5, we are getting y0, y1,y2,y7 & y10 as output in the flow, and when count is from 2 to 9 we get y15 as output and y0, y1,y2,y7 & y10 = low or '0' Under is the code that I framed, but I am getting errors, I am not sure how to frame the correct module for the same, as I just started using Verilog.

    Code Verilog - [expand]
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    module stage_1  (x0, clock_1, reset_1, y0, y1, y2, y3, y5, y7, y10, y15 );
     
    input x0; // input value from the proximity sensor
     
    input  clock_1;
    input  reset_1;
    output y0; // output of a pin connected to the close function of the mold        
    output y1; // output of a pin connected to the chain function of the mold
    output  y2; // output of a pin connected to the slide function of the mold
    output y3; // output of a pin connected to the fill function of material in mold
    output y5; // output of a pin connected to the boost function of material in mold
    output y7; // output of a pin connected to the water drain function of the mold 
    output y10; // output of a pin connected to the top heat function of the mold
    output y15; // output of a pin connected to the vacuum function of the mold
     
    reg count;
     
    always @(posedge clock_1 or posedge reset_1)
     
    begin
        if (reset_1)
        begin
            count<=count+1;
        end
    else begin
    if (x0);strong text
    if (count >= 1);  
    begin
    y0;
    end
    if (count >=2);
    begin 
    y1;
    end
    if (count >=3);
    begin 
    y2;
    end
    if (count >=4);
    begin 
    y7;
    end
    if (count ==5);
    begin 
    y10;
    end
    end
    end
    endmodule
    Last edited by FvM; 30th November 2017 at 09:18. Reason: Added syntax tags

    •   Alt30th November 2017, 08:24

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  2. #2
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    Re: implementation of output wrt clock in verilog

    1. Sorry I don't understand your specification. Please be more clear.

    2. Regarding Verilog code, first <1> has to be clarified. One thing....Wrong place to increment the count value, you never do that when reset is active.
    .....yes, I do this for fun!



    •   Alt30th November 2017, 11:17

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  3. #3
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    Re: Implementation of output wrt clock in verilog

    You have semicolons after all the if (xxxxx); which is wrong.
    You are treating Verilog like a software language.

    Here....
    Code Verilog - [expand]
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    if (count >= 1);
    begin y0; end
     
    if (count >=2);
    begin y1; end
     
    if (count >=3);
    begin y2; end
     
    if (count >=4);
    begin y7; end
     
    if (count ==5);
    begin y10; end
    These statements are all done in parallel, and the only one that takes effect will be the count >= 1 as it's only not true if the count is 0. I'm pretty sure you were thinking each of the statements would occur one after the other, even though they all happen in parallel in a single clock cycle, hence the only one that is used is the first one since it is always true (disregarding the syntax problem with using a semicolon on the end of the if, truthfully I'm not even sure how the simulation should behave with that incorrect semicolon).

    You also seem to think bare y0, y1, y2, etc are going to do anything, they won't they aren't assignments.

    Basically your code is useless, incomplete, and not even functional. You need to find a better tutorial than the garbage you typically find on the internet. I suggest you buy an actual Verilog book or look for suggestions of good tutorials (which incidentally have been posted as links on edaboard). Besides that use Verilog 2001 module port declarations, they are both more concise and they will show you've made some effort to be "more" up to date.



    •   Alt30th November 2017, 17:01

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  4. #4
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    Re: Implementation of output wrt clock in verilog

    Thank you for the advice, this code is not working. I am confused may I am short of knowledge about the Verilog. But I am working on it.
    If anyone can help with the suggestion to improve, its always welcome.



  5. #5
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    Re: implementation of output wrt clock in verilog

    Hi dpaul, for this module I have 1 bit I/O, I want make output work according to the count. I am confused with what logic I should use in order to make it work.

    Thank you



    •   Alt1st December 2017, 03:54

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  6. #6
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    Re: Implementation of output wrt clock in verilog

    I don't think Verilog allows the null statement. eg, ";;" is an error. so "if (x);" is an error. I don't think it allows a line to only be a wire. Maybe that assumes y7 is a task with zero arguments that is defined in another file. I'm not sure on that one.

    You want to have "y7 <= 1'b0;" and "y7 <= 1'b1;" for setting the value.

    "reset_1" actually is used to clock the counter, which is confusing, probably wrong, and possibly not ideal for implementation.



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