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  1. #1
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    VHDL or Verilog What is best for nested generate statement

    Hi All;
    VHDL or Verilog: What is best for nested generate statement? I need some complex nested generate statement in verilog or VHDL. But Whic is better?

    - - - Updated - - -

    I have written below code:
    Code Verilog - [expand]
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    //B1
                    if (gen_param[i*30:i*30+2]==3'b000)   // [i*30+3:i*30+18]
                        begin
                            if (gen_param[i*30+19]==1'b0) //EVEN
                                begin
                                    //B_Even
                                    B1 b1_instnc (
                                    .clk(clk),
                                    .rst(rst),
                                    .up_dn(up_dn),
                                    
                                    .d0in(downDOut0[gen_param[((i*36)+3):((i*36)+18)]]),
                                    .u0out(downUIn0[gen_param[((i*36)+3):((i*36)+18)]]),
                                    .d1in(downDOut2[gen_param[((i*36)+3):((i*36)+18)]]),
                                    .u1out(downUIn2[gen_param[((i*36)+3):((i*36)+18)]]),
                                    
                                    .d0out(downDOut0[i]),
                                    .u0in(downUIn0[i]),
                                    .d1out(downDOut1[i]),
                                    .u1in(downUIn1[i]),
                                    .d2out(downDOut2[i]),
                                    .u2in(downUIn2[i]),
                                    .d3out(downDOut3[i]),
                                    .u3in(downUIn3[i])
                                    );
                                end

    but when i try to synthesize this code i have got some errors:

    ERROR:HDLCompilers:187 - "Generator_tree_DP.v" line 241 Index in bit-select of vector wire 'downDOut0' is undefined
    ERROR:HDLCompilers:96 - "Generator_tree_DP.v" line 241 Connection to input port 'd0in' is illegal
    ERROR:HDLCompilers:187 - "Generator_tree_DP.v" line 242 Index in bit-select of vector wire 'downUIn0' is undefined
    ERROR:HDLCompilers:102 - "Generator_tree_DP.v" line 242 Connection to output port 'u0out' must be a net lvalue
    Last edited by andre_teprom; 29th November 2017 at 16:19. Reason: added QUOTE/SYNTAX tags

    •   Alt29th November 2017, 15:15

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  2. #2
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    Re: VHDL or Verilog What is best for nested generate statement

    Both languages provide generate constructs, no one would choose the HDL due to it's generate features.

    As for the syntax error in your code snippet, please provide meaningful code including the referenced variable or parameter definitions, and a complete checkable generate statement.



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