+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Junior Member level 2
    Points: 1,177, Level: 7

    Join Date
    Feb 2012
    Posts
    23
    Helped
    0 / 0
    Points
    1,177
    Level
    7

    Microsemi FPGA, remove clock buffer

    Hello, I'm using Microsemi Libero Soc v11.8 to develop VHDL code for an IGLOO nano FPGA.
    The problem I have, is that for a certain net the tool automatically adds an input clock buffer and I am not allowed to allocate the net to the pin I want, only to global clock pins.
    How can I disable this? In Xilinx there was a constraint "clock_dedicated_route = false", is there something similar in microsemi's tool?
    Thank you.
    Last edited by cocopa; 29th November 2017 at 12:16. Reason: accidentally posted

    •   Alt29th November 2017, 12:12

      advertising

        
       

  2. #2
    Super Moderator
    Points: 27,821, Level: 40
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,358
    Helped
    1540 / 1540
    Points
    27,821
    Level
    40

    Re: Microsemi FPGA, remove clock buffer

    The only reasons it would promote a pin to a clock buffer is if it was heavily loaded or is used as a clock.
    You might be able to instantiate a regular input buffer in the code and the global buffer, so it can't promote anything as you've already instantiated the correct primitives you wanted.



--[[ ]]--