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[SOLVED] CD54HC173 truth table clarification

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d123

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Hi,

I do not understand the truth table for the CD54HC173 (High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State). At all.

What combinations are needed to get a high on Q0, Q1, Q2, Q3? Can you have multiple outputs asserted? What combination(s) for all outputs to be low on power-up?

To avoid the problem of a flip flop like the CD4013 or similar randomly asserting Q or !Q on power-up, but never having the option of neither output being high, would this IC be a suitable (if slightly pricy, ~ €4 each on AVNET) alternative?

Thanks.
 

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It's 4 independent FFs with a common clock. Each Q follows it's associated D input. If you want all 4 Qs high, set all 4 Ds high. The truth table is pretty straight forward. If you want the device to power up with all outputs low, assert the MR signal on power up.
 
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    d123

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Hi,

In my eyes the truth table is ambiguous.
Especially "Q0"...
* it refers to the "state before" the clock trsnsition...
* but in the circuit above it means "the signal on pin3"

Read other '173 datasheets.

I find it less ambiguous, if they write "no change" ...

Klaus
 
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    d123

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Thanks for the replies, much appreciated.
 

Hi,

You both seem right, I think. I read the Nexperia datasheet, and the description on page 1 describes it very clearly.

One last question: The timing diagrams (p12 figure 10, and maybe but not much p11) are meaningless to my ignorance. I've never used a rising edge device, either. Can you just set clock and data high at the same time to get a high on a Q output with this device (and with other rising [or falling] edge devices)?
 

I think you need to educate yourself about flip-flops. You CANNOT set data and clock high at the same time, you must account for setup time( data must be stable for SETUP TIME prior to the clock edge). And the data must be stable for HOLD TIME after the edge. These parameters are both in the data sheet.
 
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    d123

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Hi,

Thanks. :oops: I just remembered what the Internet is for after asking here, sorry about that... Your explanation is actually quite useful to distil what I was just reading.

Sorry to go on asking about this...

So, if you had a basic circuit with no real clock and only one data signal, e.g. you weren't building a computer, you could have a longer data signal, and a delayed very short clock signal, both coming from the same input, and it would work? So long as you read the timing diagram properly and applied the times required in the Dynamic characteristics?

e.g. in crummy hobby circuit world: data input could be made longer with an rc network, and clock delayed and be made very short in duration by coming off a monostable 555?
 

Hi,

So, if you had a basic circuit with no real clock and
Maybe you don't need a D-FF...but an RS-FF...or something similar.

Klaus
 
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    d123

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I think you need to explain exactly what you're tying to do. As Klaus said, maybe you don't need a FF.
 
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    d123

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Hi,

I'm thinking of aliahsan951's tictactoe project. If the circuit uses CD4013s, then presumably at power-up and at every user-generated reset one player's LEDs or the others will be lit up, where it ideally should have no LEDs lit up at power-up and when reset, i.e. a blank tictactoe board.

...Which is why I was curious about the HC173 devices - they have the "all outputs off" feature with pins OE1 and OE2.
 

Hi,

OE just enables the output, but it does not change content of FF register.

I'd use two FF, o efoe each player, both are RESET after power up. Then they toggle according player.
But there are many possible solutions

Klaus
 
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    d123

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...After looking at his/her schematics again, I see that !Q is never used, so that must be part of the POR/reset feature that concerned me.

Anyway, it's been interesting looking at other logic devices I hadn't seen before, and simulating the SN74LS173 version of the device (it was the model available in the simulator) to "see" the rising edge concept.

Thanks.
 

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