PNR inserts more clock buffer than needed. What to do?

Good day,

I am designing a low-speed (2MHz), low-power system. During PNR , I observe that PNR inserted ~40 clock buffers for clock tree until my design is seeing ~60% power consumption due to these clock buffers. There is only ~150 registers in the design. Quick check on PrimeTime is telling that:
1. there are multiple levels of clock tree buffers;
2. most of the clock buffer only fanout to 1-2 clk cells;
3. all buffer has max_tran margin >1ns.

I shall really appreciate if anyone can comment on:
1. Is there any way to solve this? (such as set certain constraints/settings to tell Encounter not to insert so many buffers?
2. How is max_tran limit (on clock tree) determined by Encounter at 1st place? the .sdc did not specify this.

Pls forgive me if my question & description are immature as I am not familiar with PNR tool & flow.

Thanks

The design max tran is not the clock tree max tran. You can set both independently but not via SDC files as far as I know. In new Innovus flow, the command is set_ccopt_property target_max_trans 200ps. In the old CTS flow it was a property you would set in that .tcshclk file (or whatever it was called).