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[SOLVED] IOBUF primitive is not behaving the way I would like it to.

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wtr

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IOBUF primative doesn't behave the way i want

Hello all,

I'm having an issue whereby instantiation of Xilinx IOBUF leaves me with a problem, such that my command received line mirrors the command transmit line.

The truth table is a follows.
T | I | IO | O
----------------
1 | X | Z | IO
0 | 1 | 1 | 1
0 | 0 | 0 | 0

So by design the output of iobuf is mirroring the input.

In RTL this could be described as
io <= 'Z' when T else I;
O <= IO;

However this makes my separate rx_cmd (O) block trigger when it sees the tx_cmd (I) - because of the start delimiter. I could force (and have in the past) the receive block to not be enabled(hold in reset) whilst I'm transmitting, but I'd prefer to do it on the mux line.

using vhdl like
io <= 'z' when T else I;
O <= IO when not T else 'Z';

Gives the functionality I want, however it creates glitch in simulation, around the transaction/event on T.

T is driven by a valid signal in the transmit command block, it's assigned '1' as it transitions through transmit parts of the state machine.

What methods have people used the past?

Regards,
Wes
 

Re: IOBUF primative doesn't behave the way i want

using vhdl like
io <= 'z' when T else I;
O <= IO when not T else 'Z';
I don't get this code, looks wrong to me.

O is the output of the input buffer portion of the IOBUF that is driven into the fabric. There isn't a tri-state buffer there. Are you sure you understand how that primitive represents the IO cell hardware? I suggest you don't use the primitives and let the tools infer the correct logic. Just use the signal on the IO pin of the primitive anywhere you need the input and assign the IO pin with the first assignment.

To fix you problem you don't mess with the IOBUF you change your FSM that controls the rx to look at the state of the T signal to determine if it is looking at the input or not. If you just want a simple gate solution you can do something like: RX_ing <= RX_pin OR T;

It bothers me that your design seems to have a problem with this glitch, occasionally I've seen these kinds of delta cycle glitches that don't affect the simulation as the sample point of the input signal isn't on that glitch but is at the trailing edge of the signal (as it is clocked). Are you treating the RX input as falling edge clock?
 

Re: IOBUF primative doesn't behave the way i want

An internal tristate can construct be used under circumstances to make a mux, but would should be the purpose in this case? What you apparently want is to block the receiver during transmission by tying the receive signal to the inactive level. You can do it by a logic gate or by disabling the receiver logic.

In any case, it's beyond the originary function of an IOBUF.

I admit, that I'm doing something similar to the questioned internal tristate with a popular RS485 transceiver and a pull-up resistor. But that's just a trick to save an additional logic gate and has nothing to do with FPGA design.

IOBUF is reflecting the actual FPGA IO cell, everything else is additional logic.

iobuf.png
 
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    wtr

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Re: IOBUF primative doesn't behave the way i want

#3,

In the past I have disabled the receiver logic.

I guess I must concede that it's beyond the functionality of the iobuf.
 

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