josephine1234
Junior Member level 1
the code is :
and i get errors like :
1)expecting 'end', found '+'
2)unexpected token: '['
3)expecting 'endmodule', found '1'
could anyone help me?? many thanks in advance....
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 reg [63:0]sum1,sum2; initial begin sum1=mul[1][1]+mul[1][2]+mul[1][3]+mul[1][4]]+mul[1][5]+mul[1][6]+mul[1][7]+mul[1][8]+mul[2][1]+mul[2][2]+mul[2][3]+mul[2][4]]+mul[2][5] +mul[2][6]+mul[2][7]+mul[2][8]+mul[3][1]+mul[3][2]+mul[3][3]+mul[3][4]]+mul[3][5]+mul[3][6]+mul[3][7]+mul[3][8]+mul[4][1]+mul[4][2] +mul[4][3]+mul[4][4]]+mul[4][5]+mul[4][6]+mul[4][7]+mul[4][8]; $display("the value of sum is %b",sum1); end initial begin sum2=mul[1][1]+mul[1][2]+mul[1][3]+mul[1][4]]+mul[1][5]+mul[1][6]+mul[1][7]+mul[1][8]+mul[2][1]+mul[2][2]+mul[2][3]+mul[2][4]]+mul[2][5]+mul[2][6]+mul[2][7]+mul[2][8]+mul[3][1]+mul[3][2]+mul[3][3]+mul[3][4]]+mul[3][5]+mul[3][6]+mul[3][7]+mul[3][8]+mul[4][1]+mul[4][2] +mul[4][3]+mul[4][4]]+mul[4][5]+mul[4][6]+mul[4][7]; $display("the value of sum is %b",sum2); end
1)expecting 'end', found '+'
2)unexpected token: '['
3)expecting 'endmodule', found '1'
could anyone help me?? many thanks in advance....