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Error in verilog code

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josephine1234

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the code is :

Code Verilog - [expand]
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reg [63:0]sum1,sum2;
initial begin sum1=mul[1][1]+mul[1][2]+mul[1][3]+mul[1][4]]+mul[1][5]+mul[1][6]+mul[1][7]+mul[1][8]+mul[2][1]+mul[2][2]+mul[2][3]+mul[2][4]]+mul[2][5]
+mul[2][6]+mul[2][7]+mul[2][8]+mul[3][1]+mul[3][2]+mul[3][3]+mul[3][4]]+mul[3][5]+mul[3][6]+mul[3][7]+mul[3][8]+mul[4][1]+mul[4][2]
+mul[4][3]+mul[4][4]]+mul[4][5]+mul[4][6]+mul[4][7]+mul[4][8];
$display("the value of sum is %b",sum1);
end
initial begin 
 sum2=mul[1][1]+mul[1][2]+mul[1][3]+mul[1][4]]+mul[1][5]+mul[1][6]+mul[1][7]+mul[1][8]+mul[2][1]+mul[2][2]+mul[2][3]+mul[2][4]]+mul[2][5]+mul[2][6]+mul[2][7]+mul[2][8]+mul[3][1]+mul[3][2]+mul[3][3]+mul[3][4]]+mul[3][5]+mul[3][6]+mul[3][7]+mul[3][8]+mul[4][1]+mul[4][2]
+mul[4][3]+mul[4][4]]+mul[4][5]+mul[4][6]+mul[4][7];
$display("the value of sum is %b",sum2);
end

and i get errors like :
1)expecting 'end', found '+'
2)unexpected token: '['
3)expecting 'endmodule', found '1'


could anyone help me?? many thanks in advance....
 

Re: error in verilog code

Wow, thats a lot of adds.
You have a few extra ] in both initial blocks. Ill let you find them. I guess you did some copy and pasting and didnt bother to check.


To make life easier, never write terrible code like this again. Why not try using a for loop?
 

Re: error in verilog code

ive converted into a for loop... initially i used for and ended with many errors..so i decided to unroll them... and as i was rushing up i dint realize my mistake and posted it in here so that u people could help me... thanku anyways..
 

Re: error in verilog code

Error messages like "unexpected token: '['" are given with a source line number, you can easily narrow down the first error line, inspect it thoroughly and most likely fix it yourself.
 

The copy/paste of "[4]]" is the issue. you have [4]] a total of 8 times.

Depending on the tools, a for loop might not work for synthesis. I know older versions of vivado will not like a loop variable that isn't a genvar. It simply gives a warning of a simulation mismatch. It isn't clear if the initial block is generating an initial value for synthesis, or if this is just reporting logic for simulation.
 

This is why formatting of code is important.

Observe the difference between the code from above and my formatted version.

Code Verilog - [expand]
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reg [63:0] sum1;
reg [63:0] sum2;
 
initial begin
  sum1 = mul[1][1] + mul[2][1] + mul[3][1] + mul[4][1] +
         mul[1][2] + mul[2][2] + mul[3][2] + mul[4][2] +
         mul[1][3] + mul[2][3] + mul[3][3] + mul[4][3] +
         mul[1][4]] + mul[2][4]] + mul[3][4]] + mul[4][4]] +
         mul[1][5] + mul[2][5] + mul[3][5] + mul[4][5] +
         mul[1][6] + mul[2][6] + mul[3][6] + mul[4][6] +
         mul[1][7] + mul[2][7] + mul[3][7] + mul[4][7] +
         mul[1][8] + mul[2][8] + mul[3][8] + mul[4][8];
  $display("the value of sum is %b",sum1);
end
 
initial begin 
 sum2=mul[1][1]+mul[1][2]+mul[1][3]+mul[1][4]]+mul[1][5]+mul[1][6]+mul[1][7]+mul[1][8]+mul[2][1]+mul[2][2]+mul[2][3]+mul[2][4]]+mul[2][5]+mul[2][6]+mul[2][7]+mul[2][8]+mul[3][1]+mul[3][2]+mul[3][3]+mul[3][4]]+mul[3][5]+mul[3][6]+mul[3][7]+mul[3][8]+mul[4][1]+mul[4][2]
+mul[4][3]+mul[4][4]]+mul[4][5]+mul[4][6]+mul[4][7];
$display("the value of sum is %b",sum2);
end


Now isn't it easy to see the mistake?
 
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