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Problem of Offset cancellation for preamplifier of comparator?

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Electric_Shock

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I follow the output offset cancellation OOS scheme for the pre-amplier of a dynamic comparator. I use non-overlapping clock to control switches: (clk1 & clk1_n) control S1 S2 S3 S4 non-overlap with (clk2 & clk2_n) for 2 switches at Vin. But I notice that during the non-overlap time between 2 clock, the input of differential pair look like to be floating so the voltage at these nodes change undesirably like in the waveform. How do I solve this issues ? C1.JPGC2.JPGC3.JPG
 

... I notice that during the non-overlap time between 2 clock, the input of differential pair look like to be floating
Sure: actually they are floating during this interim time!

... so the voltage at these nodes change undesirably like in the waveform. How do I solve this issues ?

With one more switch, which short-circuits the inputs during CK + this interim time, i.e. it closes with CK and opens with CK_bar.
Or perhaps a small capacitance between the inputs is already sufficient?

Moreover you could try and reduce the switches' charge injection.
 

You just live with any open-circuit drift, making it as
little as possible by switch size and species. Look to
charge injection as the cause of the "kick" and to on-
resistance as the restoring force. Also beware the
accuracy of FET models when it comes to the partitioning
of gate charge when the FET is turning off, not to be
trusted. Make sure that simulator params relating to
charge and current accuracy are crunk way down
(CHGTOL, etc.) since with tiny switches, tiny charge
can make a lot of voltage.
 

Offset cancellation technique for dynamic comparator ?

I use this topology of comparator for sar adc, because it can adapt with wide range of input common mode. I want to cancel offset for this comparator. What technique can I apply for this circuit ? CC.JPGCccc.JPG
 
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