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How a setup and hold time values is decided to a flip flop?

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sarang5s5

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How a setup and hold time values is decided to a flipflop ?

How a setup and hold margins, or setup & hold values are decided to a flip flop ?
Faced this question in interviews.
 

Re: How a setup and hold time values is decided to a flipflop ?

Hi,

There are several different flip flops...I assume you should/neeed to differentiate between them.
Example: usually setup and hold times relate to a clock input...but an RS flip flop doesn't have a clock input.

What did you do to find the answer to your problem on your own?
I don't see anything.

--> If you look into a flip flop datasheet (ready to buy logic IC) then you will find informations about setup and hold times ... usually there is a timing diagram, too. What else do you need?

Klaus
 

Re: How a setup and hold time values is decided to a flipflop ?

How a setup and hold margins, or setup & hold values are decided to a flip flop ?
Faced this question in interviews.

it is not decided, it is calculated and very precisely with a lot of simulation. You set the clock waveform and the data input to switch at the same time. It will fail. Then you start moving the data away from the clock in both directions, until it works. There is your hold /setup.
 
Re: How a setup and hold time values is decided to a flipflop ?

it is not decided, it is calculated and very precisely with a lot of simulation. You set the clock waveform and the data input to switch at the same time. It will fail. Then you start moving the data away from the clock in both directions, until it works. There is your hold /setup.

Thanks for the reply.
But this method is to find out the setup/hold time of the flipflop. I am asking how that value is set while designing that flipflop ?
In hardware perspective, how is the setup and hold time set while designing the flipflop ?

An interviewer asked me the question, "How is the setup/hold value is set for a flipflop?". In other words, say I want a flipflop with setup as 1ns and hold at 0.5ns. How to construct a flipflop with these values?
 

Re: How a setup and hold time values is decided to a flipflop ?

Nobody calculate setup in such way (during characterization of std. cells). The usual approach - moving data close to the clock, and when the output delay start increasing (say in 10 %) it is the setup time.
 

Re: How a setup and hold time values is decided to a flipflop ?

Nobody calculate setup in such way (during characterization of std. cells). The usual approach - moving data close to the clock, and when the output delay start increasing (say in 10 %) it is the setup time.

are you referring to my post?
 

Re: How a setup and hold time values is decided to a flipflop ?

are you referring to my post?

yes.
Okay, as you are saying, lets say that the data is moving close to clock, and at 1ns before the clock edge, the output goes in meta-stability. This 1ns is the setup time. (Correct me if I am wrong)
Now my question is, how that 1ns margin is set to the flipflop ? Is that decided at the time of flipflop design ? or is that decided based on Master-Slave latch configuration?
Please provide the steps.

Thanks in advance.
 

Re: How a setup and hold time values is decided to a flipflop ?

are you referring to my post?

Yes. When the setup/hold is large enough, the delay of the flop remains close to the static delay. As setup/hold time reduces, the delay of the cell increases. We accept a delay that remains within 10% of the static delay. The setup/hold point where this occurs is defined as the cell specification.

The method, that you have described, is named pass/fail method. This method is obsoleted now.

- - - Updated - - -

yes.
Okay, as you are saying, lets say that the data is moving close to clock, and at 1ns before the clock edge, the output goes in meta-stability. This 1ns is the setup time. (Correct me if I am wrong)
Now my question is, how that 1ns margin is set to the flipflop ? Is that decided at the time of flipflop design ? or is that decided based on Master-Slave latch configuration?
Please provide the steps.

Thanks in advance.

The setup/hold values (measured during cell characterization) are uniq for each cell of your library. These values stored in the timing model (for example in synopsys .lib/.db files), and the static_timing_analysis tool (like primetime) is used these values during chip timing calculation.
 

Re: How a setup and hold time values is decided to a flipflop ?

Yes. When the setup/hold is large enough, the delay of the flop remains close to the static delay. As setup/hold time reduces, the delay of the cell increases. We accept a delay that remains within 10% of the static delay. The setup/hold point where this occurs is defined as the cell specification.

The method, that you have described, is named pass/fail method. This method is obsoleted now.

- - - Updated - - -



The setup/hold values (measured during cell characterization) are uniq for each cell of your library. These values stored in the timing model (for example in synopsys .lib/.db files), and the static_timing_analysis tool (like primetime) is used these values during chip timing calculation.

Thanks for your valuable responses. I appreciate the same.
But the question is still open for me. Okay let me elaborate the question. Suppose I want to design a flipflop with setup of 1ns and hold of 0.5ns. How should I proceed to design in digital manner ? or how should I design the flipflop with this configuration ?
 

Re: How a setup and hold time values is decided to a flipflop ?

If your library flip-flop has setup/hold lesser than you want to apply (you want tight the constraints), you may annotate the cell with your own values - in Synopsys it is command set_annotated_check.

If flip-flop has bigger values, than you should design the new flipflop.
 

Re: How a setup and hold time values is decided to a flipflop ?

If your library flip-flop has setup/hold lesser than you want to apply (you want tight the constraints), you may annotate the cell with your own values - in Synopsys it is command set_annotated_check.

If flip-flop has bigger values, than you should design the new flipflop.

Okay.
Is there any another method for this ?
I mean in digital way.
Suppose for example, I want to design a flipflop using NAND gates, how should I design that flipflop with setup 1ns and hold 0.5ns ? Expecting the answer in digital electronics perspective.
 

Re: How a setup and hold time values is decided to a flipflop ?

Okay.
Is there any another method for this ?
I mean in digital way.
Suppose for example, I want to design a flipflop using NAND gates, how should I design that flipflop with setup 1ns and hold 0.5ns ? Expecting the answer in digital electronics perspective.

This is backwards. Why would have these targets in the first place? The goal is to minimise setup and hold time, these are undesirable characteristics! Maybe you misinterpreted the question.

- - - Updated - - -

Yes. When the setup/hold is large enough, the delay of the flop remains close to the static delay. As setup/hold time reduces, the delay of the cell increases. We accept a delay that remains within 10% of the static delay. The setup/hold point where this occurs is defined as the cell specification.

The method, that you have described, is named pass/fail method. This method is obsoleted now.

Agreed. It also gets more complicated than that, as electrical simulation is not as perfect as we hope it to be. I am working with a certain advanced technology from a certain vendor these days, and the recommendation is to add 4 ps of hold margin for all corners, on top of whatever margining the std cell characterization team already did. But I digress, this is way beyond what the OP asked.
 

Re: How a setup and hold time values is decided to a flipflop ?

I think everyone is reading into the OPs question incorrectly, which is why the keep asking the same question over and over.

The OP (I believe) wants to know how one would design the library component of a say a DFF that has a specific setup and hold time. This is the transistor level model (the analog circuit) that DFFs are comprised of in a standard cell library. Everyone is too fixated on the 1ns setup, 0.5ns hold, which was only an example if you want to be fixated on something then how about a theoretical future process node...

Say you want your DFF to have this characteristic
25ps setup, 0ps hold

as opposed to this one
22ps setup, 3ps hold
or this one
12.5ps setup, 12.5ps hold

I don't do this kind of work, so I can't necessarily answer this with any kind of authority, but I would assume you would have to adjust the clock/data delay in the circuit by adjusting the size/speed of the transistors to move the setup-hold window (25ps) around a bit.
 

Re: How a setup and hold time values is decided to a flipflop ?

I think everyone is reading into the OPs question incorrectly, which is why the keep asking the same question over and over.

The OP (I believe) wants to know how one would design the library component of a say a DFF that has a specific setup and hold time. This is the transistor level model (the analog circuit) that DFFs are comprised of in a standard cell library. Everyone is too fixated on the 1ns setup, 0.5ns hold, which was only an example if you want to be fixated on something then how about a theoretical future process node...

Say you want your DFF to have this characteristic
25ps setup, 0ps hold

as opposed to this one
22ps setup, 3ps hold
or this one
12.5ps setup, 12.5ps hold

I don't do this kind of work, so I can't necessarily answer this with any kind of authority, but I would assume you would have to adjust the clock/data delay in the circuit by adjusting the size/speed of the transistors to move the setup-hold window (25ps) around a bit.

The general answer is to minimise both -- I struggle to find any scenario where you would want to increase either one or the other. Hold/setup optimisation can be done nearly independently in a master slave flop. Maybe the scenarios you described are not realistic. I'd have to think about it a bit more. Maybe if you had some weird clk/clkbar arrangement internally, maybe.
 

Re: How a setup and hold time values is decided to a flipflop ?

I'm specifically thinking of something like FPGAs, where the vendors regularly work to make all their FFs behave like Xns setup and 0ns hold. I'm sure that the X value is a target given to the technology node library designers to make their FFs work as fast as possible, or perhaps it's more of a here is a new process node, now just make the FFs as fast as possible, and if someone comes up with a better solution then their FFs have better performance.

That still doesn't address the fact that they might want the setup-hold window to be skewed so that there is 0ps hold, which I think might be a solution to prevent having to waste LUT resources to delay signals between FFs because the FFs have X/2 ns setup and X/2 ns hold times.

But hey, what do I know, I'm just guessing as to the whys. I don't design FPGA ICs I just use them...
 

Re: How a setup and hold time values is decided to a flipflop ?

What constitutes setup time is a question for the FF
designer.

On one hand the simplest form is, whatever makes
the FF give the right functional answer, at some later
time.

But for a synthesis based approach without detailed
parasitics and path race checking, another constraint
is that setup time makes the FF give the right answer
-by the time of its timing model-. Because close-in,
setup time begins to modulate FF delay (right before
it goes metastable and then fails to catch at all).
Depending on which you're more in love with (setup
or delay time) you can come up with different design
and design-spec choices. But it needs to be self-
consistent to support synthesis and timing closure.

You don't want much hold time (certainly, no more
than minimum FF delay because data -is- going to
change after clock (sometimes). Setup, you've got
the clock period minus interstage delays to play with.
 

Re: How a setup and hold time values is decided to a flipflop ?

Hi Sarang,

I got your question and I really appreciate if someone ask such questions. I can understand that from very first day you can't start using some Flipflop. There is always a way or say process to design a Flipflop known as specification of Flipflop.
Right now in place of helping you how Setyp and Hold Time decided for a flipflop - or say how to design a flipflop with sepecific setup/hold time, I am divinding this question in 3 sub-question and I will reply one by one.
1) Why there is a setup and hold time in a Flipflop? Or Is it constraint or its something a requirement?
2) How to change the setup and hold time of a flipflop ?
3) How to design a Flipflop from scratch with setup and hold time specification?

For #1 -- Read this. Setup and Hold Time

Once you get that - Ping me back - I will Ans #2.

Note: I dnt want to spoon feed you. So I am guiding you. Hope my approach works for you.

-Thanks
 

Re: How a setup and hold time values is decided to a flipflop ?

Some tools from vendors are there which will do the setup/hold calculation and other calculation for your cells during characterization. For setup hold calculation you can search for "Bisection method for setup calculation".
 

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