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VHDL vim recursive macro for component instantiation...a bit to gunho

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wtr

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Hello all,

I would like to know how I can prevent a recursive vim macro from blitzing through my code to the end.


Code VHDL - [expand]
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-- situation - copied a entity/component declaration. Want to turn it into a component instantiation.
entity x is
port(
sig1 : in std_logic;
sig2 : in std_logic_vector(x downto 0);
sig3 : in std_logic;
sig4 : in std_logic_vector(x downto 0);
sig5 : in std_logic;
sig6 : in std_logic_vector(x downto 0);
sig7 : out std_logic;
sig8 : out std_logic_vector(x downto 0)
);



Now in my new editor of choice (vim) I would do something like.
move cursor to sig1. init the macro. let it run until there is a space.
Code:
qq ^ywC<ctrl+r>0 => <ctrl+r>0,<esc>j@q

The problem I have is that it blitz unto the end of file and devastates other stuff. I know the j@q is responsible for this, but does anyone in this forum know how I can put a conditional statement before doing @q?

Regards,
Wes
 

Re: vhdl vim recursive macro for component instantiation...a bit to gunho

20@q will only perform the macro on 20 lines starting at the cursor.
 

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