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Missing JESD parameters in Xilinx JESD204 IP Rx!!

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I am trying to figure out how to use and configure the Xilinx JESD204B IP (v3.1 and v7.1) Rx.

I can only find the parameters - F, K, L, SCR and subclass mode as "writable" in the AXI lite register space for Rx.
The other JESD parameters are present in the register space for Rx, but are "readable" only (like CS, CF, HD, M etc.). The values are read from the ILA sequence and stored in them.


How can I configure these read-only JESD parameters? Or are they completely configured from the ILA sequence and I am not expected to set them manually?
 

My advice would be to right click on the generated ip and then subsequently select the "open ip example design".

This way you can see how the ip core is configured in a testbench. Hopefully you can then tweak it to your own desires.... Xilinx are pretty good with their documentations, so hopefully everything you need to know is provided.

Regards,
 

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