Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Split Attenuating Cap SAR ADC problem

Status
Not open for further replies.
E

elx

Newbie level 2
Joined
Nov 10, 2017
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
19
Hello
I have this problem about my SAR ADC...
sar.JPG

I tried to simulate the SAR ADC by letting an input of 1.35 V at one terminal of the comparator (net vin). I unattach the sample and hold for now.

Capture.JPG

I expect that at first cycle when SAR logic output (D7~D0) is 1000 0000, the dac output (net98) must be equal to 0.9V but it gives me 0.587 V...

What I mean is i think the SAR logic at first will have an output of 1 at bit 7 which corresponds to an analog voltage of Vref/2 (vref=1.8V) which is 0.9V... but i notice it is 0.587.

I wonder what is the reason for this. Thanks in advance.
 

Attachments

  • Capture.JPG
    Capture.JPG
    126.7 KB · Views: 70
Last edited:

If the DAC is a charge redistribution type I'd be
looking at the switching and whether there is
excess charge injection or perhaps some make-
before-break bleed-off corrupting the charge
division.

You also need to look at the DAC's loading,
maybe it's a simple charge division problem.
Use some controlled sources to buffer between
stages and see.

I've got no way of knowing whether things are
otherwise logically correct.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top