[SOLVED] Bootstrap capacitor after long time without getting charged

Hello everyone,

Let's consider a situation where the bootstrap capacitor is NOT being charged during an OFF time (because the output current in e.g. a buck converter has reached 0) because the output diode is off.

The capacitor must have enough energy in order to get through that off time (without being charged) and still have energy to power the FET at the end of the idle state and to keep it ON during the on time (worst case, when the duty cycle is maximum).
After all this, the voltage of the cap must still be above the UVLO of the driver in order to not get powered off.

All this came up because I disagree with **broken link removed**.

In the paragraph right above the equation 32, TI says this (I quote):
"The bootstrap capacitor must supply all the usual discharge current components and store enough energy to be able to turn-on the switch at the end of the idle period."

However, my understanding is that one should add, at the end of TI's phrase, the italic phrase I said at the beginning and repeat here:
"and to keep it ON during the on time"

By my understanding, the equation 32 should be rewritten as in the picture below.

I am looking forward for your opinions.
Thank you for your time !

I agree with your analysis that you may need a little extra to turn it ON and keep it ON. But I think Dmax may not be needed. That would be too conservative. Dmin may be better since if you are off for a long time the converter may not go into Dmax unless there is something wrong with the loop compensation. Dmin fdrv should be enough to allow enough current into the inductor so that when the inductor current decays again to 0 that time is sufficient to charge the boost cap back up again.

I think, the worst case is when the diode current is first off for multiple cycles (32) and then the switch is turned on for a longer time (31). Respectively, the minimum bootstrap capacitor is the sum of both values. The time doesn't depend on fDRV or DMAX because it's not periodical and probably extended over multiple fDRV cycles.

FvM said:

Respectively, the minimum bootstrap capacitor is the sum of both values.

Click to expand...

Now that you say it, I agree. However, I want to be sure in 1 little detail:
Sum of (32) and (31) gives in the numerator 2*Qg. I think it should be 1*Qg. What do you think ?

I also agree with you that I should have added the Qrr (reverse recovery charge of bootstrap diode) in my post #1's equation, which I did not.

FvM said:

I think, the worst case is when the diode current is first off for multiple cycles (32) and then the switch is turned on for a longer time (31). Respectively, the minimum bootstrap capacitor is the sum of both values. The time doesn't depend on fDRV or DMAX because it's not periodical and probably extended over multiple fDRV cycles.

Click to expand...

Although I think this case should not happen but depends on your control loop. If you want to do that Qg should be considered only once to turn the high side FET on.

I suggest to put the question less theoretical.

If long (> 1/fDRV) on or off cycles can happen, quiescent current is usually the dominant factor. Gate or even diode reverse recovery charge can be usually ignored in this case.

If the supposed worst case (long zero diode current period with succeeding long on period) is feasible, depends on the control loop and load current dynamic. Obviously we are not talking about steady state (as already mentioned in the TI application note).

Hi,

quiescent current is usually the dominant factor

Click to expand...

I agree.
And often the main "quiescent current" is caused by a (useless) gate-source resistor that is shown in many doubtful "internet schematics"...while this resistor doesn´t exist in the manufcaturer´s datasheets.

Klaus

KlausST said:

And often the main "quiescent current" is caused by a (useless) gate-source resistor that is shown in many doubtful "internet schematics"...while this resistor doesn´t exist in the manufcaturer´s datasheets.

Click to expand...

IR21xx drivers does not show any needed gate-soruce resistor, but then the manufacturer itself uses it in their application examples e.g. using the IR2110 here:
https://design.infineon.com/tinadem...trial|Power|&file=power_IR2110_HB_OptiMOS.tsc

IR21xx drivers does not show any needed gate-soruce resistor, but then the manufacturer itself uses it in their application examples e.g. using the IR2110 here:
**broken link removed**

Click to expand...

Whoever sketched the schematic, he's apparently not familiar with IR2110 internal circuit and actual behavior. I'm not aware of any original IRF data sheet or application not suggesting the gate source resistors.

You'll see that the low-side transistor of both drivers starts to pull down gate voltage above about 1V supply voltage respectively 1.6V Vgs, if no other voltage supplies the driver. The pull-down path stays activated until the respective supply voltage reaches the UVLO threshold.

If you have MOSFET with very low threshold voltage, you might intend a lower clamp voltage, but a 1k resistor is surely not effective in this regard, you would need an external circuit with a depletion mode PFET shorting Vgs.

FvM said:

You'll see that the low-side transistor of both drivers starts to pull down gate voltage above about 1V supply voltage respectively 1.6V Vgs, if no other voltage supplies the driver. The pull-down path stays activated until the respective supply voltage reaches the UVLO threshold.

Click to expand...

I don't see it . I do not see that 1.6 V Vgs.

This is what I see:
If no other voltage is supplying the driver, then the FETs act as floating and each Vds will have half the supply i.e. 25 V.
The parasitic capacitors of each FET forms then a voltage divider, giving about 25*(6 pF)/(600 pF)=0.25 V gate-source for all FETs, if there was no Rgs. But Rgs pulls it down to 0 Vgs.

I'm reporting measurements with real IR2110, not discussing theoretical conclusions. Nevertheless the behaviour can be explained, I think.

Can you explain the behaviour, please ? :-D

You have this output stage topology, shown for LS but almost similar for HS driver:



Substrate diodes will clamp LO to VCC + 0.6 V. For VCC levels above MOSFET Vth and below UV Detect threshold, LO is pulled low by NMOS output transistor.