msdarvishi
Full Member level 4
Dear all,
I am working with a Zedboard (xc7z020clg484) and I intend to integrate SEM to this FPGA. I did a lot of trials but I could not succeed since the rx and tx ports are not available in PL part. I tried to create block design and import a Zenq prcessing system plus a GPIO AXI to make a bridge between rx and tx in PS part to the PL. But the bitstream does not generate and it fails due to the unconstrained IO ports. Can anyone has an idea or steategy or have done it before to share its files with me?
Kind replies and helps are appreciated.
Regards,
I am working with a Zedboard (xc7z020clg484) and I intend to integrate SEM to this FPGA. I did a lot of trials but I could not succeed since the rx and tx ports are not available in PL part. I tried to create block design and import a Zenq prcessing system plus a GPIO AXI to make a bridge between rx and tx in PS part to the PL. But the bitstream does not generate and it fails due to the unconstrained IO ports. Can anyone has an idea or steategy or have done it before to share its files with me?
Kind replies and helps are appreciated.
Regards,