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    SEM IP instantiation on Zedboard and rx-tx ports problem

    Dear all,

    I am working with a Zedboard (xc7z020clg484) and I intend to integrate SEM to this FPGA. I did a lot of trials but I could not succeed since the rx and tx ports are not available in PL part. I tried to create block design and import a Zenq prcessing system plus a GPIO AXI to make a bridge between rx and tx in PS part to the PL. But the bitstream does not generate and it fails due to the unconstrained IO ports. Can anyone has an idea or steategy or have done it before to share its files with me?

    Kind replies and helps are appreciated.

    Regards,

    •   Alt14th November 2017, 02:00

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    Re: SEM IP instantiation on Zedboard and rx-tx ports problem

    The SEM has RX and TX connected to pins on the PL side, it doesn't connect to the PS RX TX unless you modify the design, which might not be possible if it is encrypted.

    You could just jumper the pins of the SEM onto external RX and TX lines that do connect to the PS.

    What is the point of using the SEM with a non-rad hard Zynq PS? that is going to experience a lot of faults.



    •   Alt14th November 2017, 02:52

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    Re: SEM IP instantiation on Zedboard and rx-tx ports problem

    Quote Originally Posted by ads-ee View Post
    The SEM has RX and TX connected to pins on the PL side, it doesn't connect to the PS RX TX unless you modify the design, which might not be possible if it is encrypted.

    You could just jumper the pins of the SEM onto external RX and TX lines that do connect to the PS.

    What is the point of using the SEM with a non-rad hard Zynq PS? that is going to experience a lot of faults.

    Dear ads-ee,

    Thanks for your reply. You probably did not get my point. Your statement :

    You could just jumper the pins of the SEM onto external RX and TX lines that do connect to the PS.
    the problem is here! There are no external pins on the Zedboard to be used as the RX and TX. Please have a look on page 14 of the attached PDF file to see what I mean.

    I also found the following XDC constraint file for PS part of this Zedboard and I added to my XDC file and did implementation but nothing happened and I could not generate bistream due to the error concerning the RX and TX port location.

    https://github.com/develone/zynq-zc7...onstraints.xdc

    Do you have any idea?zedboard_ug.pdf



    •   Alt14th November 2017, 20:00

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    Re: SEM IP instantiation on Zedboard and rx-tx ports problem

    Isn't there two UARTs on the Zynq PS? You can always change the connections to the USB-UART bridge to instead route the UART to the PL. Or you can create a separate fabric based UART for the PS and add it to the processor system design, which can then be connected to the SEM.

    A co-worker recently did a design with 3 UART ports on a Zynq, two dedicated PS UARTs and one located in the fabric using some off the shelf dev board.



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    Re: SEM IP instantiation on Zedboard and rx-tx ports problem

    Quote Originally Posted by ads-ee View Post
    Isn't there two UARTs on the Zynq PS? You can always change the connections to the USB-UART bridge to instead route the UART to the PL. Or you can create a separate fabric based UART for the PS and add it to the processor system design, which can then be connected to the SEM.

    A co-worker recently did a design with 3 UART ports on a Zynq, two dedicated PS UARTs and one located in the fabric using some off the shelf dev board.
    YES, there are two UARTs (UART0 and UART1) connected to PS of Zynq in Zedboard. But as you said, the problem is that how to change the connections to the USB-UART bridge to instead route the UART to the PL. This is what I do not know how to do!!!!



    •   Alt14th November 2017, 23:02

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    Re: SEM IP instantiation on Zedboard and rx-tx ports problem

    There is a big switch like structure in the PS that routes the various resources to either dedicated pins or the PL. You have to change the setting of that big switch structure.

    Look at figure 1.1 on pg27 in https://www.xilinx.com/support/docum...q-7000-TRM.pdf on the left side is the EMIO, that is how you access the UART that goes to pins.

    I believe you have to modify the PS system design to enable the EMIO to route the UART to the fabric (I'll admit I haven't done this type of design myself).



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