Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VHDL coding techniques

Status
Not open for further replies.

manishpatkar

Junior Member level 1
Joined
Oct 6, 2017
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
159
inside a process how to wait for a rising egde or a falling edge ? or can we wait for certain fixed time ?

eg.

Code:
process (IDC)
begin
if(rising_edge(IDC)) then

     if(rising_edge(C)) then
        if(Tee= '0') then
          wait until ??;
          
          end if;
 

Re: vhdl coding techniques

Hi,

Rising edge of which signal?


Rising edge of "Tee":
* use a DFF to store the state of "Tee". Result = "Tee_before"
* use an AND gate: rising_edge = Tee AND NOT Tee_before.

Klaus
 

Re: vhdl coding techniques

inside a process how to wait for a rising edge or a falling edge ?
Normally rising edges are used. If a signal is included in the sensitivity list of process, the process will be executed wherever there is a change in the included signal. Considering you are writing this process for a design that will be synthesized, you can write
Code:
    process(clk_i, rst_n_i)
    begin
        if rst_n_i = '0' then -- async reset signal
            -- assign reset values of signals used; 
            
        elsif rising_edge(clk_i) then

        -- write your logic here

        end if;
    end process;

or can we wait for certain fixed time ?
You can, but when designing a hardware model which will NOT be synthesized. Normally this is done in test benches.
Code:
    wait for 10 ns;           -- wait for a flat time of 10 nanoseconds
    wait until falling_edge(clk_i); -- wait until the falling edge of clk_i
    wait until clk_i'event;            -- wait until the rising or falling edge of clk_i

Your code snippet makes me suspicious! Are you modeling something that will be synthesized or are you doing some test-bench work?
Read a good VHDL book.
 
Last edited:
Re: vhdl coding techniques

we have a idc clock , tff flipflop(half of the frequency of idc) and a carry signal which gets high with certain offset. I want to geerate a new tff signal(tff_new) such that
1. if the carry signal goes high when tff=1 , the tff_new would be inverted wrt to tff next rising edge of tff.

2. if the carry signal goes high when tff=0 , the tff_new would be inverted wrt to tff after second rising edge of tff

we have been failing to get this logic implemented .. please give us idea on how to approach it! IMG-20171113-WA0008.jpg
 

Attachments

  • IMG_20171113_195708_HDR (2).jpg
    IMG_20171113_195708_HDR (2).jpg
    481.9 KB · Views: 54

Re: vhdl coding techniques

Any special reason to use T-ff and not a D-ff?
Is this s homework exercise where you are given to design only using T-ff?
 

Re: vhdl coding techniques

we have a idc clock , tff flipflop(half of the frequency of idc) and a carry signal which gets high with certain offset. I want to geerate a new tff signal(tff_new) such that
1. if the carry signal goes high when tff=1 , the tff_new would be inverted wrt to tff next rising edge of tff.

2. if the carry signal goes high when tff=0 , the tff_new would be inverted wrt to tff after second rising edge of tff

we have been failing to get this logic implemented .. please give us idea on how to approach it!View attachment 142489

Code:
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 11/13/2017 04:17:10 PM
-- Design Name: 
-- Module Name: dco - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dco is
    Port ( idc : in STD_LOGIC;
          -- start: in STD_LOGIC;
           tff : in STD_LOGIC;
           c : in STD_LOGIC;
           b : in STD_LOGIC;
           tffnew : out STD_LOGIC;
           idout : out STD_LOGIC);
end dco;

architecture Behavioral of dco is
shared variable temp : integer := 2;
begin

--process(start)
--begin
--tffnew <= tff;
--end process;

process(c)

begin
if(rising_edge(c)) then
    if(tff='1') then
        temp:=1;
    end if;
    if(tff='0') then
        temp:=0;
    end if;
end if;
end process;


process(tff)
begin
if(rising_edge(tff) or falling_edge(tff)) then
    if(temp=0) then
        tffnew <= not tff;
        temp:=2;
    elsif(temp=1) then
        tffnew <= not tff;
        temp:=2;
     elsif(temp=2) then
        tffnew <= tff;
    end if;
      
end if;
end process;
--		--IDOUT <= (not IDC) and (not tffnew);
end Behavioral;


sir, i am a beginner and trying to model a dco . above code is something that i worked
 

Re: vhdl coding techniques

Hi,

TFF (toggle flip flop) makes no sense.

Still unclear what exactly you wanted to do.

--> show a draft with all your involved input signals.
--> use a second color to draw the expected output signal.

Klaus
 

Re: vhdl coding techniques

sir, i am a beginner and trying to model a dco . above code is something that i worked

Restrict yourself to work with D-ff. Initially restrict yourself to only working with the rising of the clock.
As pointed out in #7, it is also not clear to me what you want to do.
Now you need to clearly describe what you want to do.
 

Re: vhdl coding techniques

tff is the output of toggle flipflop with T=1 that we used as a input to test for now! so basically this for DCO for a adpll .. In our code we ae trying to generate a tff_new which changes due to carry and borrow inputs.
just to make things clear i have attached a copy of the slide we are refering to..Screenshot (81).pngScreenshot (82).png
 

Re: vhdl coding techniques

Hi,

Why don´t you answer the questions?
I don´t see how your attached documents relate to the problem. Please explain.
We recommended not to use TFF. We recommended to use DFF. Nobody knows why you still use TFF.

Klaus
 

Re: vhdl coding techniques

OP, a TFF requires extra logic to implement in an FPGA, DFFs already exists in the FPGA fabric. As others have stated us DFF only.

Also I recommend you answer the questions for clarification that have been posted, otherwise you will soon have nobody answering any of your questions.

- - - Updated - - -

inside a process how to wait for a rising egde or a falling edge ? or can we wait for certain fixed time ?

eg.

Code:
process (IDC)
begin
if(rising_edge(IDC)) then

     if(rising_edge(C)) then
        if(Tee= '0') then
          wait until ??;
          
          end if;

Also the above code is impossible to implement in any FPGA as you have two "clocks" in the process, i.e. rising_edge(IDC) and rising_edge(C).
 

Re: vhdl coding techniques

my first post is a part of the second post.. i want to implement dco(second post with diagrams) , i could implement if i could use a way to delay it so asked the first post(on how to delay inside a process)...
i am not able to code to get the desired output of dco (explained in those two attachments).. i need help or idea to code dco for adpll (behaviour explained in the attachment above)
... i am not sure how to use dflipflop to get the desired output (my second post)... tflipflop is a previous block in my project so the input is named as tff..
hope this clears it!
 

Re: vhdl coding techniques

DFF in VHDL

Code VHDL - [expand]
1
2
3
4
process (clk)
begin
  q <= d;
end



TFF in VHDL (implemented with DFF)

Code VHDL - [expand]
1
2
3
4
5
6
process (clk)
begin
  if (t) then
    q <= not q;
  end if;
end


So a TFF is just a DFF with input being the Q output inverted and an enable.

Note, this code does not account for any reset that may be required to ensure a simulation runs correctly.
 

Re: vhdl coding techniques

Also the above code is impossible to implement in any FPGA as you have two "clocks" in the process, i.e. rising_edge(IDC) and rising_edge(C).
The nested clocks won't achieve useful behavior in simulation either. Notice that the inner rising_edge() event only becomes true if both clock edges occur in the same delta cycle, which is almost impossible.

Also don't mix "if" and "wait until" event statements.
 

Re: vhdl coding techniques

my first post is a part of the second post.. i want to implement dco(second post with diagrams) , i could implement if i could use a way to delay it so asked the first post(on how to delay inside a process)...
i am not able to code to get the desired output of dco (explained in those two attachments).. i need help or idea to code dco for adpll (behaviour explained in the attachment above)
... i am not sure how to use dflipflop to get the desired output (my second post)... tflipflop is a previous block in my project so the input is named as tff..
hope this clears it!

Dear OP, begin with something very very basic.
Forget about what is there in those PDFs you have posted.

Try to implement a 3 bit up counter using D-ffs. A 3 bit counter (output of 3 D-ffs) will increment in value with every rising edge of the clock.
Do that and test your basic understanding.
 

Re: vhdl coding techniques

Dear op,

Regardless of going down the rabbit hole regarding what flip flop you're using.

Consider the following

process with sensitivity list cannot have wait statements.
process without sensitivity lists can have wait statements.

You would use the wait on, wait until and wait for statements usually for testbenching because for the most part people consider it non synthesible.
However a single wait until statement can be synthesised because it's considered equivalent to a clocked process. - in some tools.
The wait on statement can be synthesised because some tools consider it to be the sensitivity list to a combinatorial process.
 

Re: vhdl coding techniques

Dear op,

Regardless of going down the rabbit hole regarding what flip flop you're using.

Consider the following

process with sensitivity list cannot have wait statements.
process without sensitivity lists can have wait statements.

You would use the wait on, wait until and wait for statements usually for testbenching because for the most part people consider it non synthesible.
However a single wait until statement can be synthesised because it's considered equivalent to a clocked process. - in some tools.
The wait on statement can be synthesised because some tools consider it to be the sensitivity list to a combinatorial process.

You just made OP's head explode. He is not in a position where he should be playing with wait statements, he is too green for that. OP has to learn the basic of the basic: coding templates for combinational and sequential logic.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top