Driver strength and slew rate control

Hi everyone,

I would like to know how both of these concepts relates to each other since from .y understanding, the driver strength is the one who controls the slew rate. This is specially seen on gpios.

From my understanding, if you have a strong driver strength, your slew rate will be high.

Now if you look at some MCUs/FPGAs their gpios slew rate are allowed to be controlled.

But like I mentioned above, the slew rate can be controlled by drive strength for the load. That is, high slew rate, high drive strength for more current.

Then, what's the concept of that slew rate can controlled separately with drive strength? Why there is a choice of slew rate and drive strength together?

Regards.

Hi,

Slow slew rate reduces EMI.

And it may improve when multiple data lines are switched at the same time. Like a wide address bus or data bus.
Sometimes you need high drive strength (DC) to control a LED directly...but it doesn't need high slew rate.

There are many reasons to use the one or the other setup. It depends on the application.

Klaus

An output driver without dedicated slew rate control switches fast, the output current rise/fall time could be e.g. 0.5 or 1 ns. The drive strength (output current) control can be used to adjust the rise time with capacitive load, a separate slew rate reduction feature reduces the current rise/fall time itself.

Thanks for both replies, however, this remains a bit confusing for me.

How can you have slew-rate control and also driver strength control? And from what I read, both at the same time? Can't get it. How is there a choice of slew rate and drive strength together?

Regarding the driver strength, from my understanding, you are increasing the amount of current being pumped into the capacitor that it is driving, correct?
Now, if you think about the slew-rate control, basically you are controlling the dv/dt on the output node.

Now how can you have high drive strength and control the slew rate? Unless the slew-rate has priority/super impose a limit.

Can you draw a picture?

In addition to this, do you know any circuit that does this? For clarification.

FvM, "a separate slew rate reduction feature reduces the current rise/fall time itself." but I thought that slew-rate was related to the voltage. How can this influence the current rise/fall time?

R.

I thought that slew-rate was related to the voltage. How can this influence the current rise/fall time?

Click to expand...

Not necessarily. Slew-rate can be defined for current as well.

The basic question is how the programmable drive strength and slew rate feature are implemented.

Programmable drive strength is usually realized by multiple parallel connected output transistors and respective selection logic.

Slew rate can be either reduced driving the output transistor gates with lower current or a ramped voltage. Depending on the gate driver impedance, you get mainly constant output di/dt or dv/dt by miller effect.

I hope, the explanations clarifies at least that output current and slew rate can be controlled separately.

I see.

So basically you have got a programmable driver strength by changing the number of parallel MOSFETs in parallel and then with some sort of circuitry you might control the slew rate of the current (which I presume affects also the voltage?). The control slew rat doesn't mean the you will limit the amount of current being pumped at the output, you will make it take longer to get to the maximum value. Is that it?

Can you exemplify a way of implementing this? You said that by controlling the gate and it makes sense. Is he any other way? For example can you mess with the output directly also?

In the below scheme, C1 is provides output voltage independent current slew rate reduction while Miller capacitor C2 is targeting to a specific output voltage slew rate.



Real MOSFETs expose certain amounts of Cgs and Cgd, they might be under circumstances sufficient to implement the intended function.

Hi FvM,

That's a very nice exemplification.

Now, you can implement the circuit with C2, without C1 correct? If it is correct, this means that the implementation would be targeting only the output voltage slew-rate. Correct?

But one thing that still confuses me is the following: Say that you had a programmable driver strength, and you program it to drive at maximum current. Still, can you control the voltage slew-rate? Aren't they inter-related? That is, you increase the drive strength (current capability) to drive some load and by doing that the slew-rate will increase right? I still can't get the drive strength (current capability to drive the LOAD) is indepedent of the voltage slew-rate.

Slew rate can be controlled internally by adding series
gate resistance to the final stage FETs (as is done in
power circuits at the power MOSFET gate). This uses
Miller current to self-limit slew rate. DC drive strength
is unaffected except during the transition.

A gate's DC drive strength varies a lot with VDD, temp,
process all by itself. Using a better controlled / less
PVT sensitive element(s) like Rs and Cs (gate ox is a
prime control-point) eliminates much of that scatter.

I see your point. Now what you mean by using Rs and Cs?

Do you have any circuit example?

Drive strength is essentially a DC parameter, it's usually specified as output current achievable at a certain voltage drop. Drive strength is of course related to maximum switching speed with a specific capacitive load, programmable drive strength is an effective means to adjust it.

Programmable slew rate is a way to reduce the switching speed without affecting the maximum output current.