Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Moved]How to convert a vhdl code to verilog code

Status
Not open for further replies.

nagulapatigirireddy

Newbie level 5
Joined
Nov 11, 2017
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
65
this is the code for converting decimal to binary in vhdl.How to cinvert a vhdl code to verilog code


Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
library IEEE;
 use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
--
 
entity decimal is
end decimal;
 
architecture beh of decimal is
signal  my_sulv1 : std_ulogic_vector(15 downto 0);
signal my_int : integer range 0 to 100;
signal  my_sulv2 : std_ulogic_vector(15 downto 0);
--
begin
my_int <= to_integer(unsigned(my_sulv1));
 
my_sulv2 <= std_ulogic_vector(to_unsigned(my_int, 16));
end beh;

 
Last edited by a moderator:

Re: How to cinvert a vhdl code to verilog code

I believe the question involves a misunderstanding. The VHDL integer type isn't specifically related to decimal number representation. Integer quantities can be represented with different base, e.g. decimal, hexadecimal, octal, binary.

Integer is a general-purpose type that can be either used abstracted from logic hardware, or infer signed and unsigned numbers in hardware.

The shown code doesn't involve an actual conversion, except for a number truncation to 7 bit unsigned (in hardware synthesis) or 0 to 100 range check in simulation.
 

Re: How to cinvert a vhdl code to verilog code

Other than the correctness of the code, I have inhibitions on the free software/s that claim to convert VHDL to Verilog and vice-versa (#2).
Basically the best way is to do it manually. But this not necessary (if this is not your homework assignment) as most simulators and synth engines support mixed mode HDL designs.
Also you have posted this in the wrong sub-forum.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top