# [Moved]How to convert a vhdl code to verilog code

1. ## [Moved]How to convert a vhdl code to verilog code

this is the code for converting decimal to binary in vhdl.How to cinvert a vhdl code to verilog code

```Code VHDL - [expand]1
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library IEEE;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
--

entity decimal is
end decimal;

architecture beh of decimal is
signal  my_sulv1 : std_ulogic_vector(15 downto 0);
signal my_int : integer range 0 to 100;
signal  my_sulv2 : std_ulogic_vector(15 downto 0);
--
begin
my_int <= to_integer(unsigned(my_sulv1));

my_sulv2 <= std_ulogic_vector(to_unsigned(my_int, 16));
end beh;```

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2. ## Re: How to cinvert a vhdl code to verilog code

You can use for example this translator: http://www.edautils.com/vhdl2verilog.html

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3. ## Re: How to cinvert a vhdl code to verilog code

I believe the question involves a misunderstanding. The VHDL integer type isn't specifically related to decimal number representation. Integer quantities can be represented with different base, e.g. decimal, hexadecimal, octal, binary.

Integer is a general-purpose type that can be either used abstracted from logic hardware, or infer signed and unsigned numbers in hardware.

The shown code doesn't involve an actual conversion, except for a number truncation to 7 bit unsigned (in hardware synthesis) or 0 to 100 range check in simulation.

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4. ## Re: How to cinvert a vhdl code to verilog code

Other than the correctness of the code, I have inhibitions on the free software/s that claim to convert VHDL to Verilog and vice-versa (#2).
Basically the best way is to do it manually. But this not necessary (if this is not your homework assignment) as most simulators and synth engines support mixed mode HDL designs.
Also you have posted this in the wrong sub-forum.

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