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    MAX10 PLL External Clock Output

    Hello there,
    I'm using the 10M08SCE144A7G FPGA.

    In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters.
    There is only 1 output of this type with this FPGA.

    I'll like to know if there is any recommendations using this output signal to fed 3 diferents Analog to Digital Converters ? (fanout , layout for exemple)
    Is this a good way to do it ?

    Maybe driving the PLL output to 3 diferents standard fast I/O pins (1 pin for 1 DAC) is a better design ?

    Thank you for your help.
    Julien.

    •   Alt9th November 2017, 14:35

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    Re: MAX10 PLL External Clock Output

    FPGAs can easily have anywhere form 50-300ps of package delay difference between pins (even adjacent pins).

    I recommend using the PLL output clock and running it through a clock distribution IC e.g. RoboClock.


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    Re: MAX10 PLL External Clock Output

    Hi,

    as so often - it depends on the signal requirement. What is it used for? What frequency, what logic levels, what timing requirements...

    Klaus
    Please donīt contact me via PM, because there is no time to response to them. Thank you.



    •   Alt9th November 2017, 17:39

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    Re: MAX10 PLL External Clock Output

    Quote Originally Posted by KlausST View Post
    Hi,

    as so often - it depends on the signal requirement. What is it used for? What frequency, what logic levels, what timing requirements...

    Klaus
    Hi,
    The output signal of the FPGA internal PLL will be use to give the clock (100 MHz to 130 MHz) to 3 Analog to Digital Converters (AD9433).
    The output level is 0 V / +5 V.
    I don't know if there is any particular requirements using this ADC (Didn't see anything in the datasheet).
    Thank you for your help.



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    Re: MAX10 PLL External Clock Output

    For AD9433, I would use a high level (e.g. +/- 2.5 V or +/- 3.3V) differential clock output, capacitive coupling to match the common mode range, source side 2x50 series termination, differential 100 ohms party line passing all three ADCs, 100 ohm end termination.

    The output level is 0 V / +5 V.
    No. Read the datasheet. 5V will hardly fit a FPGA or other high speed data sink.

    Only the analog input uses 5V. The clock input is 5V capable, but can be supplied with lower logic level, utilizing the differential input buffer and capacitive coupling if necessary.



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    Re: MAX10 PLL External Clock Output

    Hi,

    Hard job.
    High sampling rate, 3 devices in parallel, databus 3 x parallel...expect trouble in PCB layout routing and data processing.

    I've done a project with similar requirement. I've chosen LTC2172. One device, 4 channel simultaneous sampling with LVDS interface.
    I think this is more simple and the more reliable, too. Take a look at it's datasheet, maybe it fits your needs.

    Klaus
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    Re: MAX10 PLL External Clock Output

    Most convincing point for me would be that LTC2174-12 (4x12-bit 100 MHz) price is less than two AD9433-100. But it's 1.8 versus 5V technology which impacts on the analog design in several regards. The respective 600 MHz LVDS data rate is already at the edge of MAX10 speed, 750 MHz for the 125 MHz ADC version far beyond.

    Interfacing AD9433 100/125 MHz fully parallel interface is relative easy in comparison.



    •   Alt11th November 2017, 11:39

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    Re: MAX10 PLL External Clock Output

    Quote Originally Posted by ads-ee View Post
    FPGAs can easily have anywhere form 50-300ps of package delay difference between pins (even adjacent pins).

    I recommend using the PLL output clock and running it through a clock distribution IC e.g. RoboClock.
    Good tip ! I didn't know those circuits actually exists.
    To run my tests I'm gonna use a component of this familly (Texas Instruments): "CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family"

    I'll keep you posted of the tests and solution I'll be choosing.



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