Biasing a common-mode level for differential pair

I'm designing a pre-amp for a comparator used in 10bit SAR-ADC. I want to bias a CM level 0.5mV for the input of differential pair so that the pair is always ON with all input. How can I do that ? which topology should I choose ?

Differential amplifiers tend to include a common mode
feedback section which does exactly this.

You should understand that keeping the front end "lit"
does not require a particular common mode per se, but
rather that one, the other or both exceeds VT of the
front end FETs "comfortably".

A rail-rail input stage is another option, which is OK
with any common mode position (even past the rails,
in some cases). However gain may vary significantly as
you approach the rails.

An option could be to "throw away" some dynamic range
and by constraining input / output swing, constrain (but
not pin, necessarily) the common mode voltage. This
costs SNR probably.

Might also consider auto-zero clocked comparators
where the front end is capacitor blocked, and the null
phase probably puts the common mode somewhere
nice to begin with (like, you build a common mode
reference for the switch-to of the null / shorting phase).

I'd be going through Red Rag back issues on IEEEXplore
and then looking for ways to not pay IEEE to look at the
more likely circuit design papers (Google the "title", head
to your university engineering library, etc.).

The SAR ADCs I've worked with (older, piece-part assys
+/-10V) all worked about a 0.000 (GND) pivot point with
DAC pulling low and trimmed resistors (on the DAC, for
the purpose) pulling to the +10.000V Vref and determining
bipolar or unipolar operation. The comparator and DAC had
negative supply for the tail currents, which may not suit a
modern positive-only CMOS design. But you don't say what
such concerns / parameters are in this case.