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What does ALIAS block mean in a RTL schematic?

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shmoib

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xilinx rtl schematic alias

dear all,
when i run synthesize for my VHDL code and check its RTL schematic on ISE6.2i i found some blocks called 'ALIAS', does that mean anything wrong?

i attached the RTL schematic
 

Re: synthesize

u should share the schematic file instead of the word file...

so mayb we can run compilation/simulation to check for u...

regards,
sp
 

Re: synthesize

here is the code, it also contain the same problem althought it is very simple
 

Re: synthesize

actually i cant c any block name "alias" in ur provided doc....can u?..too small..cant c the block name..

i read the code...it is simple one....n it shouldnt hav any error....

i try compile using quartus 2(sorry, i dunno how-to on xilinx) no error found...
and the RTL i get is...see att whether it match urs...
 

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    shmoib

    Points: 2
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Re: synthesize

thnks for ur help, but when i synthesize it on ISE of xilinix i found that alias
anyway, i need u to check this code for me too, as i got same problems with it
 

Re: synthesize

Is the synthesizer inferring FSMs ?

I generally get ALIAS signals on the RTL schematics when I build FSMs. This is normal.
 

Re: synthesize

yes, i got same problem with FSM but i got same problem too with that simple code that i posted here
 

Re: synthesize

sorry,,,i dunno wad is the "ALIAS" signal means.... so cannot help... can anyone explain...

hehe,,,too bad,,,


regards,
sp
 

    S

    shmoib

    Points: 2
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Re: synthesize

As I don't have a RAR program handy at the moment, I looked at the Word file. There is nothing wrong with the ALIAS signals. What you're getting is normal.

An "alias" is an alternate name. The RTL circuit is an FSM. The signals don't correspond to VHDL signal names. The name of the signal is actually the name of an enumeration that was used to define a state in the HDL code.

For example, if you define several states:

type dev_state is (idle, run, done);

then VHDL defines idle, run, and done as constants - not signals.

The synthesizer infers from your coding style that these constants are being used to drive an FSM, and they are translated into actual signals with an assumed name (an alias), which is the same as the state name.
 

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    shmoib

    Points: 2
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