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Sending data sequentially

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beginner_EDA

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Hi,
I have 64 bit serial bus where I am suppose to send data serially and I tried as follows:

Code Verilog - [expand]
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reg         [15:0]                  gen_data_reg_7_6 = 16'd0;
   reg         [15:0]                  gen_data_reg_5_4 = 16'd0;
   reg         [15:0]                  gen_data_reg_3_2 = 16'd0;
   reg         [15:0]                  gen_data_reg_1_0 = 16'd0;
 
  reg         [1:0]                   i = 2'b00;
 
always @(posedge aclk)
  begin
 
         i <= i + 1;
         if (i == 2'b00)
         begin               
               gen_data_reg_1_0 <= 16'h2000;
               gen_data_reg_3_2 <= 16'hb505; 
               gen_data_reg_5_4 <= 16'h0000;
               gen_data_reg_7_6 <= 16'h0201;
        end
        else if (i == 2'b01)
         begin
               gen_data_reg_1_0 <= 16'h8aa1;
               gen_data_reg_3_2 <= 16'hfea9;
               gen_data_reg_5_4 <= 16'h9df2;
               gen_data_reg_7_6 <= 16'h00e0;
        end
         else if (i == 2'b10)
                begin
                      gen_data_reg_1_0 <= 16'hfc00;
                      gen_data_reg_3_2 <= 16'h0494;
                      gen_data_reg_5_4 <= 16'h0000;
                      gen_data_reg_7_6 <= 16'h0016;
               end
          else if (i == 2'b11)
               begin
                     gen_data_reg_1_0 <= 16'h0309;
                     gen_data_reg_3_2 <= 16'h00e0;
                     gen_data_reg_5_4 <= 16'hfc00;
                     gen_data_reg_7_6 <= 16'hfc00;
              end
       
      
 
    end



but the last 64 bit data(condition for else if (i == 2'b11)) is not coming.

What is wrong here? Is there any other way?
 

Hi,

can´t you use the simulator to see what happens?

Btw: You say "64 bit serial bus", but isn´t it a "64 bit parallel bus"?

Klaus
 

As per your program, you will only get the following condition passed..
if (i == 2'b00)
begin
gen_data_reg_1_0 <= 16'h2000;
gen_data_reg_3_2 <= 16'hb505;
gen_data_reg_5_4 <= 16'h0000;
gen_data_reg_7_6 <= 16'h0201;
end

I dont know how you are getting the passed conditions for 2b01 and 2b10...

Where you are manipulating 'i'?
 

Hi,

can´t you use the simulator to see what happens?

Btw: You say "64 bit serial bus", but isn´t it a "64 bit parallel bus"?

Klaus

In simulation, it is OK. See attachment.
 

Attachments

  • sim.jpg
    sim.jpg
    240.4 KB · Views: 55

This is a 64 bit parallel bus - there is nothing serial about it.
So in simulation it works - whats the problem on hardware?
 

Hi,

If simulation is OK, then I expect the reality is OK, too.
Bus type: Now I´m about sure that it is called a 64 bit wide parallel bus with SDR (single data rate)

What is your serial clock?

Maybe it´s a transmission line problem or a receiver problem - in real world.
How did you do the real world testing?

Klaus
 

If you want serial you normally shift out of your parallel register.

Look at parallel in serial out (PISO)

From what I've read you are correctly assigning parallel data to your registers based on your I select. (You could also use a case statement here.)

On a side note in your simulation the value of I says it's a 32 bit register. This is common of integers.
I also see the you are getting values expected for i == 2'b11, however this is all happening a clock cycle after the conditional statement.
 

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