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Converting Layout in Cadence Virtuoso to GDSII format

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bio_man

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Hi,

I want to convert my layout to GDSII required by MOSIS. I am using Cadence Virtuoso and I get the gds file by doing :
from CIW:
File >> Export >> Stream

The gds file I got is only 50kB of size! is that usually the case, i feel this is not too much? my layout is 4mm2 and I have over 500 transistors and some big capacitors.


The second question, I want to see the GDS graphically and/or 3D. I found this software (https://www.youtube.com/watch?v=F4EArOqNNSU) but it requires a Process Definition file, I tried to make one by translating the technology (C5 technology) layer map into their way of writing the file but did not work, I always got an error that there is no substrate layer? although I added it into the txt file.

I attach both the Process layer map from MOSIS and GDS3D software process definition file and their readme file. I hope one can suggest what I need to do to make this readable to GDS3D software.
 

Attachments

  • ProcessCode.txt
    347 bytes · Views: 127
  • ProcessDef.txt
    3.5 KB · Views: 80
  • GDS3D_Error.png
    GDS3D_Error.png
    28.7 KB · Views: 185
Last edited:

I like this simple GDSII viewer (2D only):
https://www.owlvision.org/

Thanks for sharing this software. I tried my GDS file and I can see only resistors but other layers are not shown! Maybe the way I generated the GDS file is not right?

In Virtuoso CIW, I used File--> Export --> Stream

- - - Updated - - -

BTW, Is there any difference between GDS and GDSII format? the file I have is Layout.gds but the examples present in OwlVision GDS viewer is inv.gdsii
 

Attachments

  • GDS_view.png
    GDS_view.png
    66.8 KB · Views: 352

Calling out the right layerTable is critical to exporting
clean and complete. Look to the stream log file for any
messages about stuff not being exported, because of
invalid layer/purpose pair etc.

On the import side, layers also need to be assigned and
turned visible in whatever viewer. You can also stream
in the created GDS file (to a new library and using the
blessed layerTable (or techfile)) and look at it in Cadence.
Could also then rerun LVS on the streamed-back-in file
to ensure integrity.
 

You must have made a mistake when exporting the design, the layer mapping is wrong. Check the log, it is pretty easy to figure out which layers are wrong.
 
Yes, in the stream options there was no layer map specified. I selected the auto option (screenshot attached) because I don't know how to access the layer map for the technology I am using. I already specified the technology. So, I got the GDS file and using the viewer it looks ok.

My followup question here, what is the file I need for Via Map in the stream options? because it's highlighted clearly that it would be better to add viaMap. what do you think?

Also, is there a way to count the number of transistors in my design?
 

Attachments

  • Exporting_GDSII_0.png
    Exporting_GDSII_0.png
    148.1 KB · Views: 250
  • Exporting_GDSII_1.png
    Exporting_GDSII_1.png
    80.5 KB · Views: 310
  • Exporting_GDSII_2.png
    Exporting_GDSII_2.png
    189.1 KB · Views: 245
  • Exporting_GDSII_3.png
    Exporting_GDSII_3.png
    113.7 KB · Views: 246

auto option is not a good idea. search through your pdk folders, you must have some layermap somewhere.
 

auto option is not a good idea. search through your pdk folders, you must have some layermap somewhere.

what is the extension of layermap file is it xxxx.il like the attached screenshot? I know xxxx.tf is the techFile which we don't need here, right?

and for both, it did not work. I always got nothing in my GDS. However, when I used the auto option, I got all devices just looks like my layout in Cadence L-editor.
 

Attachments

  • LayerMapFile.png
    LayerMapFile.png
    60.1 KB · Views: 184

There are two possibilities, either there is a layerTable file
or the layers info resides in the techfile (then you check
the box for that rather than inserting the layertable path
in the form field).

.il is the suffix for SKILL script files. The technology file
ought to be something like techfile.tf (? - been a while).

I'd start with going to the process directory and doing
a file search for "layer*" and "tech*" and see what turns
up, where. Seems like "auto" finds {something} and may
look right, may even be right. Streaming in the layout
and running LVS against the original schematic is a good
test.
 
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