promach
Advanced Member level 4
I have few questions regarding the modified PMOS load circuitry for Figure 15.18(c)
1) Why does M3 and M4 consume only a voltage headroom equal to |VDS3,4| after the addition of NMOS source follower ?
2) When M3 operates at the edge of the triode region, why is small-signal resistance of the load roughly equal to 1/gm3 ? I suppose it should be 1/gm5 ?
3) Could anyone elaborate on "the finite output resistance of the follower may yield an inductive behavior for the load" ?
Screenshot retrieved from Razavi Design of Analog CMOS Integrated Circuits 2nd Edition book.
1) Why does M3 and M4 consume only a voltage headroom equal to |VDS3,4| after the addition of NMOS source follower ?
2) When M3 operates at the edge of the triode region, why is small-signal resistance of the load roughly equal to 1/gm3 ? I suppose it should be 1/gm5 ?
3) Could anyone elaborate on "the finite output resistance of the follower may yield an inductive behavior for the load" ?
Screenshot retrieved from Razavi Design of Analog CMOS Integrated Circuits 2nd Edition book.