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    LCD code for fpga virtex 6

    i want a vhdl code to use lcd of an fpga virtex 6 .
    could anyone help me and give me this code?
    thanks

    •   Alt6th November 2017, 12:39

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    Re: lcd code for fpga virtex 6

    Quote Originally Posted by moonshine8995 View Post
    i want a vhdl code to use lcd of an fpga virtex 6 .
    could anyone help me and give me this code?
    thanks
    No, nobody can help, but you could help yourself by...
    a) using google to try and find some VHDL code to drive an LCD.
    b) post the code you wrote that doesn't work along with the LCD datasheet/part number/etc. and a question that we can answer.

    This forum is not intended for getting free code for all your projects. There are other sites devoted to obtaining IP, free or otherwise.



    •   Alt6th November 2017, 17:39

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    Re: lcd code for fpga virtex 6

    thank you.
    this is the code i find.
    it was a verilog code and i change it to vhdl.
    now i have some problem in converting it.
    [syntax=vhdl]LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.ALL;
    USE ieee.numeric_std.ALL;

    entity lcd is

    port(
    clk, RxD : in std_logic;
    LCD_RS, LCD_RW, LCD_E : inout std_logic;
    LCD_DataBus : out std_logic_vector(7 downto 0);

    RxD_data_ready :in std_logic;
    RxD_data : inout std_logic_vector(7 downto 0)
    );
    end lcd;

    architecture behav of lcd is
    signal count : integer;
    signal Received_Escape : std_logic;
    signal Received_Data : std_logic;
    signal LCD_instruction : std_logic;
    begin
    LCD_RW <= '0';
    LCD_DataBus <= RxD_data;

    Received_Escape <= (RxD_data_ready) and (RxD_data:='0');
    Received_Data <=(RxD_data_ready) and (RxD_data>0);

    process(clk)
    begin
    if rising_edge(clk) then
    if(Received_Data='1') then
    count <= count + 1;
    if(count>0) then
    count <= count + 1;
    -- activate LCD_E for 6 clocks, so at 25MHz, that's 6x40ns=240ns
    end if;
    end if;
    end if;
    end process;
    process(clk)
    begin
    if rising_edge(clk) then
    if(LCD_E ='0')then
    LCD_E <= Received_Data;
    if (count/=6)then
    LCD_E <= std_logic_vector(to_unsigned(count, 1));

    --reg LCD_instruction;
    end if;
    end if;
    end if;
    end process;
    process (clk)
    begin
    if rising_edge(clk) then

    if(LCD_instruction='0')then
    LCD_instruction <= Received_Escape;
    if (count/=7)then
    LCD_instruction <= std_logic_vector(to_unsigned(count, 1));
    end if;
    end if;
    end if;
    end process;
    LCD_RS <= not(LCD_instruction);

    end behav;[/syntax]
    here are the vhdl code errors and i think if i correct these more errors will be found.
    and this is the verilog code i find :
    [syntax=verilog]
    module LCDmodule(clk, RxD, LCD_RS, LCD_RW, LCD_E, LCD_DataBus);
    input clk, RxD;
    output LCD_RS, LCD_RW, LCD_E;
    output [7:0] LCD_DataBus;

    wire RxD_data_ready;
    wire [7:0] RxD_data;
    async_receiver deserialer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));

    assign LCD_RW = 0;
    assign LCD_DataBus = RxD_data;

    wire Received_Escape = RxD_data_ready & (RxD_data==0);
    wire Received_Data = RxD_data_ready & (RxD_data!=0);

    reg [2:0] count;
    always @(posedge clk) if(Received_Data | (count!=0)) count <= count + 1;

    // activate LCD_E for 6 clocks, so at 25MHz, that's 6x40ns=240ns
    reg LCD_E;
    always @(posedge clk)
    if(LCD_E==0)
    LCD_E <= Received_Data;
    else
    LCD_E <= (count!=6);

    reg LCD_instruction;
    always @(posedge clk)
    if(LCD_instruction==0)
    LCD_instruction <= Received_Escape;
    else
    LCD_instruction <= (count!=7);

    assign LCD_RS = ~LCD_instruction;

    endmodule[/syntax]

    - - - Updated - - -

    i forgo to attach the error.
    this is the error for line
    LCD_E <= std_logic_vector(to_unsigned(count, 1));
    and line
    LCD_instruction <= std_logic_vector(to_unsigned(count, 1));
    Type conversion (to ieee.std_logic_1164.STD_LOGIC_VECTOR) conflicts with expected type ieee.std_logic_1164.STD_LOGIC
    and these are the errors
    near ":=": (vcom-1576) expecting ')'.
    for line
    Received_Escape <= (RxD_data_ready) and (RxD_data:='0');
    and
    (vcom-1581) No feasible entries for infix operator 'and'.
    and
    Type error resolving infix expression "and" as type ieee.std_logic_1164.STD_LOGIC.
    for line
    Received_Data <=(RxD_data_ready) and (RxD_data>0);
    thanks for helping me.
    Last edited by ads-ee; 7th November 2017 at 16:48. Reason: change quote to syntax tags for easier reading



    •   Alt7th November 2017, 12:41

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    Re: lcd code for fpga virtex 6

    LCD_E is a std_logic, not a std_logic_vector. Hence you cannot assign a std_logic_vector to it.
    := is the variable assignment operator, not the equality (=) operator.

    Why are the LCD_ ports inout? if you need to read them internally, then create a local signal to do it. inout should really only be used for true inout ports, like tri-state buffer.
    RxD_Data does not need to be inout - just in



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