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Simple questions about synchronizer

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promach

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1) For table 1 of Berkelay Paper , why "Input must be valid for at least two clock periods in the new domain." ?

The explanation:

the width of the input pulse must be greater than the period of the synchronizer clock plus the required hold time of the first synchronizer flip-flop. The safest pulse width is twice the synchronizer clock period.

Could anyone tell why it has to do with hold time of the first synchronizer flip-flop ?

2) For pulse synchronizer or what we known as toggle synchronizer, I do not understand the explanation highlighted in yellow that is given below:

This problem is more severe when the clock period of input pulse is greater than twice the synchronizer clock period

lXrCw.jpg
 

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