+ Post New Thread
Results 1 to 10 of 10
  1. #1
    Member level 3
    Points: 788, Level: 6

    Join Date
    May 2015
    Posts
    59
    Helped
    0 / 0
    Points
    788
    Level
    6

    inout port in an inner component

    I have read many questions regarding inout port in vhdl. Given the details, I am a bit hesitated to use a tristate buffer for that. Now my question is like this:
    I have three components A,B,C in a hierarchy of D.
    D has a signal X : STD_LOGIC_VECTOR(99 downto 0).
    The bits of this vector get modified by all the three components (A,B,C) at different times (Not simultaneously). But each component may change 1 or 2 or 3 or 4 of its bits.
    Is there a way to realize this without using an INOUT port in these inner components?

  2. #2
    Advanced Member level 3
    Points: 4,711, Level: 16

    Join Date
    Feb 2015
    Posts
    782
    Helped
    230 / 230
    Points
    4,711
    Level
    16

    Re: inout port in an inner component

    sure?

    each component has an output, X_a, X_b, X_c. some logic you have not defined creates X_sel from these and X_in. This is used as an input to A,B,C. X_sel then connects to X_out due to VHDL's restrictions on output ports and internal connections.

    There are other options. The above is fairly general. There may be better ways to do this based on the exact problem.


    1 members found this post helpful.

    •   Alt4th November 2017, 06:16

      advertising

        
       

  3. #3
    Advanced Member level 5
    Points: 34,872, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,390
    Helped
    1861 / 1861
    Points
    34,872
    Level
    45

    Re: inout port in an inner component

    Each bit of X is independent of all other bits, so you can drive them all how you like (within reason). It would be fairly normal to have different parts of a bus change based on different inputs.
    Never use inout unless you explicitly want a tri-state buffer, and then, these will only work if connected directly to an output pin of a device, otherwise they get changed to separate in and out muxes.


    1 members found this post helpful.

    •   Alt4th November 2017, 08:01

      advertising

        
       

  4. #4
    Member level 3
    Points: 788, Level: 6

    Join Date
    May 2015
    Posts
    59
    Helped
    0 / 0
    Points
    788
    Level
    6

    Re: inout port in an inner component

    each component has an output, X_a, X_b, X_c. some logic you have not defined creates X_sel from these and X_in. This is used as an input to A,B,C. X_sel then connects to X_out due to VHDL's restrictions on output ports and internal connections.
    Then outside the port mapping of component, I have to assign X_out into X_in?



    •   Alt4th November 2017, 08:51

      advertising

        
       

  5. #5
    Advanced Member level 5
    Points: 34,872, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,390
    Helped
    1861 / 1861
    Points
    34,872
    Level
    45

    Re: inout port in an inner component

    Why would you do that? Your original post doesnt make huge sense - why not write a code snippet to try and show what you're trying to do?



  6. #6
    Member level 3
    Points: 788, Level: 6

    Join Date
    May 2015
    Posts
    59
    Helped
    0 / 0
    Points
    788
    Level
    6

    Re: inout port in an inner component

    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    
    entity arch_D IS
    GENERIC (N : INTEGER := 16);
    Port ( clk,en_ref : in STD_LOGIC;
             valid,ref_end : out STD_LOGIC;
             byte_out : out STD_LOGIC_VECTOR (7 downto 0));
    end arch_D;
    architecture Behavioral of arch_D is
    COMPONENT comp_A is
        GENERIC (N : INTEGER := 16);
        Port ( clk,en : in STD_LOGIC;
               b0 : in STD_LOGIC_VECTOR(N*N/4-1 downto 0);
               valid : in STD_LOGIC := '0';
               b1 : out STD_LOGIC_VECTOR (N*N/4-1 downto 0));
    end COMPONENT comp_A;
    COMPONENT comp_B is
        GENERIC (N : integer := 16);
        Port ( clk,en : in STD_LOGIC;
               b0 : in STD_LOGIC_VECTOR(N*N/4-1 downto 0);
               valid : in STD_LOGIC := '0';
               b1 : out STD_LOGIC_VECTOR (N*N/4-1 downto 0));
    end COMPONENT comp_B;
    -------SIGNAL Declaration----
    signal b0,b1,b2 : STD_LOGIC_VECTOR(N*N/4-1 downto 0);
    begin
    compA : comp_A GENERIC MAP (N) PORT MAP (clk,en,b0,valid,b1);
    compB : comp_B GENERIC MAP (N) PORT MAP (clk,en,b0,valid,b2);
    mux : mux PORT MAP (b1,b2,sel,b0);
    end Behavioral;
    Please ignore all other signals except b0,b1,b3...
    My aim in this code is to update b0, so I input b0 into both components, generate b1 and b2 (updated versions of b0). And then b0 is replaced by the updated version.
    Am I right? Is there any better way to do so without using inner INOUT?



  7. #7
    Advanced Member level 5
    Points: 34,872, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,390
    Helped
    1861 / 1861
    Points
    34,872
    Level
    45

    Re: inout port in an inner component

    Im not quite sure what answer you're after. And what do you mean by "replaced by updated version"? signals are just like wires in a circuit, and take whatever value is assigned to them.

    I have no idea what any of these components do, but I assume it is some kind of oscillating system as it has no external inputs?



  8. #8
    Member level 3
    Points: 788, Level: 6

    Join Date
    May 2015
    Posts
    59
    Helped
    0 / 0
    Points
    788
    Level
    6

    Re: inout port in an inner component

    I have no idea what any of these components do, but I assume it is some kind of oscillating system as it has no external inputs?
    One sure thing it does is that it modifies the contents in b0 and I want b0 to reflect the changes. Please ignore the functionality of any component, as it is a part of a large design and to make it simple I have mentioned here only two components.
    And what do you mean by "replaced by updated version"? signals are just like wires in a circuit, and take whatever value is assigned to them.
    I can not send my b0 into the component and get is modified straightaway. So I am using b1 and b2 to carry the modified value of b0 out of the components. At the end I want b0 itself to reflect its modified value.



    •   Alt4th November 2017, 13:42

      advertising

        
       

  9. #9
    Advanced Member level 5
    Points: 34,872, Level: 45
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,390
    Helped
    1861 / 1861
    Points
    34,872
    Level
    45

    Re: inout port in an inner component

    Neither comp 0 or comp 1 will modify b0 as it is an input, their b1 output could be some modified version of b0 if you want.

    Maybe you need to draw this as a circuit, rather than as code, to try and visualise what's going on.



  10. #10
    Advanced Member level 3
    Points: 4,711, Level: 16

    Join Date
    Feb 2015
    Posts
    782
    Helped
    230 / 230
    Points
    4,711
    Level
    16

    Re: inout port in an inner component

    "updating b0" sounds like you are trying to describe some form of combinatorial loop. In either case, it is a weird thing to do. you would normally have a new value like b4 be generated by the mux. On some clock edge, b4 might be used to update b0.

    if you are trying to create a combinatorial loop or a system, you would normally still have a b4 and then write some logic to describe how b4 is used to update b0. This will generate a synthesis warning as it is a combinatorial loop. You would also be responsible for determining if the resulting circuit ever has memory or ever is unstable. I'm not sure if the tools know how to evaluate the circuit for static timing analysis either, so you might also need to manually specify timing based on how many times a path re-enters the circuit.

    My guess is that you don't understand digital design and are trying to force b0 to work in the way you want it to. Other posters know that this doesn't work or make sense and thus have a hard time understanding what you are doing. I strongly suspect this is the case and that you have not considered using a clock along with the mux output in order to update b0. Your lack of mentioning an intentional combinatorial loop or needing N stages of a loop to be unrolled makes me suspect this as well.



--[[ ]]--