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    VHDL: Can 'transaction = '1' with 'active = false in the same delta?

    Hi All

    Im trying to see if Ive got a bug in ActiveHDL
    For a given signal s, could it be possible for s'transaction = '1' and s'active = false in a given delta?
    From my understanding, s'active and s'transaction are very similar, so should always match.

    Thanks for opinions

    •   Alt3rd November 2017, 14:53

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    Re: VHDL: Can 'transaction = '1' with 'active = false in the same delta?

    Quote Originally Posted by TrickyDicky View Post
    For a given signal s, could it be possible for s'transaction = '1' and s'active = false in a given delta?
    Yes. The opposite can happen as well i.e. s'transaction='0' and s'active=true.
    'active : True if there is a transaction (assignment to the signal) in the current simulation cycle, otherwise false.
    'transaction: bit that changes its value each time there is a transaction in the signal.

    It can be that you made a transaction in the signal and hence the bit changed to 1 (i.e. s'transaction='1') and in that same delta s'active=true, but in the next one s'active=false while there is no other transaction in the signal, hence s'transaction still at 1.

    That is my understanding.



    •   Alt3rd November 2017, 15:47

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    Re: VHDL: Can 'transaction = '1' with 'active = false in the same delta?

    But a 'transaction occurs during a signal assignment, hence also 'active should also be true.
    Your explanation doesnt really explain how you can get 'transaction='1' and 'active = false

    My Doulos Guide says:
    'active = TRUE if and only if there is a transaction on S in the current delta.

    and the LRM:
    As simulation time advances, the transactions in the projected output waveform of a given driver (see
    14.7.2) will each, in succession, become the value of the driver. When a driver acquires a new value in this
    way or as a result of a force or deposit scheduled for the driver, regardless of whether the new value is
    different from the previous value, that driver is said to be active during that simulation cycle. For the
    purposes of defining driver activity, a driver acquiring a value from a null transaction is assumed to have
    acquired a new value. A signal is said to be active during a given simulation cycle if
    — One of its sources is active.
    — One of its subelements is active.
    — The signal is named in the formal part of an association element in a port association list and the
    corresponding actual is active.
    — The signal is a subelement of a resolved signal and the resolved signal is active.
    — A force, a deposit, or a release is scheduled for the signal.
    — The signal is a subelement of another signal for which a force or a deposit is scheduled.
    So this implies you can only be 'active if there is also a 'transaction. Remember that 'active is a function and 'transaction is a signal. you can be sensitive to 'transaction, but no 'active.

    - - - Updated - - -

    Actually - I guess you can:

    Code:
    s <= '1';
    wait for 0 ns;
    s <= '1';
    wait for 0 ns;
    This would make 'transaction toggle => '1' then '0', but 'active = high for both deltas



    •   Alt3rd November 2017, 16:02

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    Re: VHDL: Can 'transaction = '1' with 'active = false in the same delta?

    Quote Originally Posted by TrickyDicky View Post
    This would make 'transaction toggle => '1' then '0', but 'active = high for both deltas
    That is what I have said in the previous post.

    When you first assign you put 'transaction to '1'. Then, in the next delta 'transaction is still '1' if you do not assign anything, or '0' if you have assigned anything. 'transaction toggles, as you say.

    'active stays true only for the assignment's delta.



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    Re: VHDL: Can 'transaction = '1' with 'active = false in the same delta?

    This all comes about because it's friday and I didnt realise about the toggle. I had the following code:

    Code VHDL - [expand]
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    wait on s1'transaction, s2'transaction;
     
    if s1'transaction then ...
    if s2'transaction then..

    when I should have had

    Code VHDL - [expand]
    1
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    wait on s1'transaction, s2'transaction;
     
    if s1'active then ...
    if s2'active then..

    Maybe Ill be more alert next week!



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