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How to do so? I could only manage to use hvt and lvt cells for my design in 90nm technology. I am not able to figure out on how to specify to the synopsys compiler that it needs to use lvt on critical path and hvt elsewhere. Can you suggest something?
You could force the tool to use a faster data-path structure to help to reach the timing.
The Synthesis & PnR tools are able to choose the fastest cells if there is enough place to put the cells in the area.
Do you have an issue at the synthesis or during the PnR?
I did the two-pass sythesis method and loaded the lvt library first and a hvt library later. This gave me just the switching power with a value and the remaining power values were 0.