In an Nmos, why is the P-substrate(Body) lightly doped compared to its S and D

in the above diagram (NMOS), the source and drain are highly doped (n+), where as the p-substrate (body) is lightly doped (p-), can anyone tell me why the body region (channel region) is lightly doped. Is it because we need to achieve a low threshold voltage?

I've heard from other sources that, the p-substrate incase of Nmos or the N-well incase of the Pmos is lightly doped, because it reduces the noise and leakage current. Could you please tell me how it reduces the leakage current or reduces the noise.

Thanks,
Arokia

Arokia said:

... why the body region (channel region) is lightly doped.

Click to expand...

Any doping change in semiconductors usually is done either by diffusion (formerly) or by implantation (nowadays, +diffusion) of appropriate ions which - in case of building a region of opposite doping like source/drain - have to over-compensate the original doping concentration.

Hence the substrate/well doping concentration is always lower than that of the newly generated regions of opposite doping polarity.

This is a very good question, even though some may view it as naive.

Doping in source / drain region is required mainly to provide a low-resistivity connection from the metallization / contacts to the channel - that's why it is made as high as possible (up to a solid solubility limit).
Very often, source/drain regions are silicided, i.e. converted to almost metal-like material, at least at the surface of silicon, to reduce the resistance.
Also, people are working on metal source/drain, for that purpose.

To the contrary, channel doping is used mainly to control the threshold voltage of the MOSFET, so its doping is selected with thereshold voltage being the target.
Open any book on semiconductor devices (for example - Physics of semiconductor devices by Simon Sze, a classic), and you will see charts showing Vt dependence on doping (and other parameters - like gate oxide thickness).

That being said, doping profile in a MOSFET is engineered to meet many other requirements, like leakage (drain to substrate, like GIDL effect), or source-to drain in the off state (DIBL effect), mobility (retrograde profiles), etc.

In modern MOSFETs, doping is not uniform, and is created by several different implants.

Yes, you see "lightly doped drain" features (meant to make
the drain "deplete away from the gate" enhancing high
voltage reliability (HCI) and you also may see "halo" that
-raises- body doping locally to enhance that effect.

The flip side can be, if you push back the S/D by the
depletion region bias, you can get to a "failure to hook
up" the channel at low applied voltages (either the gate
has to work harder to pull it back into ohmic connection,
or you need more drain bias, or both). This is bad news
for low power analog, linearity of on resistance and so
on. This is an interplay between dopings (straight and
angled, what you get is not what you see looking down
the Z axis at CAD system polygons), spacer geometry,
gate doping (a co-player w/ well doping in setting VT,
and do not forget about poly depletion).