manishpatkar
Junior Member level 1
i am trrying to design a DCO for adpll based on increment decrement counter. i am able to understand what to do but can't convert logic into vhdl code..
i have attached my reference for implementation and the partial code along with tflipflop that is being used:
once carry is set high ,need to traverse to second rising edge in temp_1 and reverse(or some math) the wave to desired output and vice versa for a borrow high! i cant seem to convert this into code!
please let me know if there's a way to do this or other logic to implemet this!
tff is here !
partial code to begin to identify rising edges etc (without the operation to reverese the wave)
attached images of ppt that i am refering for the implemenation and images of simulation fo the partial code(for reference )
i have attached my reference for implementation and the partial code along with tflipflop that is being used:
once carry is set high ,need to traverse to second rising edge in temp_1 and reverse(or some math) the wave to desired output and vice versa for a borrow high! i cant seem to convert this into code!
please let me know if there's a way to do this or other logic to implemet this!
tff is here !
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tff is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
QT : out STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal qt_loc : std_logic :='0';
begin
process (CLK)
begin
if rising_edge(CLK) then
if RESET='1' then
QT <= '0';
else
qt_loc <= not qt_loc;
QT <= qt_loc;
end if;
end if;
end process;
end Behavioral;
partial code to begin to identify rising edges etc (without the operation to reverese the wave)
Code:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dco1 is
Port ( IDC : in STD_LOGIC;
C : in STD_LOGIC;
B : in STD_LOGIC;
IDOUT : out STD_LOGIC);
end dco1;
architecture Behavioral of dco1 is
component tff is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
QT : out STD_LOGIC);
end component;
signal RT : std_logic := '0';
signal Tout : std_logic := '0';
signal temp_1 :std_logic;
signal temp_2 :std_logic;
signal a1 :std_logic := '0';
signal b1 :std_logic :='0';
signal c1 :std_logic:='0';
begin
t0: Tff port map (CLK=>IDC, RESET=>RT,QT=>temp_1);
process (IDC, C, B)
begin
if (rising_edge(IDC)) then
a1 <= '1';
elsif(falling_edge(IDC)) then
a1 <='0';
end if;
if (rising_edge(C)) then
b1 <= '1';
elsif(falling_edge(C)) then
b1 <='0';
end if;
if (rising_edge(B)) then
c1 <= '1';
elsif(falling_edge(C)) then
c1 <='0';
end if;
--temp_2 <= Tout and temp_1;
--IDOUT <= (not IDC) and (not temp_2);
end process;
end Behavioral;
attached images of ppt that i am refering for the implemenation and images of simulation fo the partial code(for reference )