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[SOLVED] VHDL - Illegal choice in record aggregate.

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wtr

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Hello all,
I want to declare a record constant.

I have a signal within a record that is a an array of bytes.


Code VHDL - [expand]
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type byte_ar_t is array (integer range <>) of byte_t;
 
type x is record
 sig1 : byte_t;
 sig2 : byte_ar_t(4 downto 1);
 sig3 : byte_ar_t(4 downto 1);
 sig4 : byte_ar_t(4 downto 1);
end record;
 
constant x_default : x := (
sig1 => (others => '0'), --fine
sig2 => (x"00", x"01, x"03, x"00"), --fine
sig3 => (others => (others => '0'), -- fine
sig4(4) => (others => '0'),  -- error
sig4(3) => X"01", -- error
sig4(2) => x"00", -- error
sig4(1) => x"11" -- error
);

Error message is
(vcom-1067) Illegal choice (indexed name) in record aggregate. Legal choices are element_simple_name and OTHERS.

You can do this for an entity declaration can you not? You can do a signal assignment such as x <= val(1).ue;

Have I just got my syntax messed up?

- - - Updated - - -

I think I answered my own question.
Code VHDL - [expand]
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sig4           => (
sig4(4) =>(others => '0'),  
sig4(3) =>x"01",
sig4(2) =>x"00",
sig4(1) =>x"11",
                );


Nope!! scratch that...this just lead to further errors later on.
 

Yes - you cannot slice an array inside a record assignment - you need to specify the entire field in 1 go when you assigning the record.
 

Okay! I accept this as a limitation for a record assignment!
Therefore...
Expanding on methodology in https://www.edaboard.com/showthread.php?t=30735 , I should be able to generate a function that can take my (not true) 2d array and assign it to a record.

For example
Code VHDL - [expand]
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type byte_ar_t is array (integer range <>) of byte_t;
subtype ecsd_word_t is byte_ar_t(511 downto 0);
----------------------
    type ecsd_reg_t is
        record
            ext_security_err         : byte_t; -- To indicate an securrity errors
            s_cmd_set                : byte_t; -- cmd set supported by device (emmc/mmc)
            hpi_features             : byte_t; -- fb form cmd12/13
            bkops_support            : byte_t; -- Background operations
            max_packed_rd            : byte_t; -- cmds allowed to be packed into rd cmd
            max_packed_wr            : byte_t; -- ditto, min 3.
            data_tag_support         : byte_t; -- is data tag supported?
            tag_unit_size            : byte_t; -- size of tag in bytes
            reg_res_size             : byte_t; -- max quantity of resources
            context_capabilities     : byte_t; -- capabilities 
            large_unit_size_m1       : byte_t; -- size of largue unit minus 1
            ext_support              : byte_t; -- extended partition attribute support
            supported_modes          : byte_t; -- Does it support FFU, VSM?
            ffu_features             : byte_t; -- mode op codes ya/nay?
            operation_cd_timeout     : byte_t; -- watchdog for switch cmd 6
            ffu_arg                  : byte_ar_t(4 downto 1); --dword_T; --tell host arguement to use
-------------------------------------
 
function get_ecsd_reg_f (arg : csd_word_t) return ecsd_reg_t is
    variable ecsd_reg : ecsd_reg_t;
    begin
            ecsd_reg.ext_security_err             := arg(505);
            ecsd_reg.s_cmd_set                    := arg(504);
            ecsd_reg.hpi_features                 := arg(503);
            ecsd_reg.bkops_support                := arg(502);
            ecsd_reg.max_packed_rd                := arg(501);
            ecsd_reg.max_packed_wr                := arg(500);
            ecsd_reg.data_tag_support             := arg(499);
            ecsd_reg.ffu_arg                      := arg(490 downto 487); --the effort to enable this
 

yes, not quite clear what all the types are, but makes sense.

Usually, it's just easier to name the functions the functions like this (as I have seen in many places):
function to_record( s : std_logic_vector ) return my_record_t;
function to_slv( r : my_record_t ) return std_logic_vector;

Its clearer to the user whats going on and not have to dig through your package to find the correct name. Luckily, because VHDL allows function overloading by parameter types, you can have a pair of these for each of your record types, and compiler will just pick the correct one.
 

TrickyDicky said:
Yes - you cannot slice an array inside a record assignment - you need to specify the entire field in 1 go when you assigning the record.
Click to expand...

I have subsequently looked into this and I can slice an array within a record assignment...

Check it out VV
Code VHDL - [expand]
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constant x_default : x := (
    sig1 => (others => '0'),
    sig2 => (x"00", x"01", x"03", x"00"),
    sig3 => (others => (others => '0')),
    sig4 => (1=> X"00", 3=> x"12", 2=> x"00", 4=> x"11"));


This is very powerful because now I can index my assignments register maps, etc shall be a doodle

check em V

Code VHDL - [expand]
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constant x_default : x := (
    sig1 => (others => '0'),
    sig2 => (x"00", x"01", x"03", x"00"),
    sig3 => (others => (others => '0')),
    sig4 => (3=> x"12", others => x"00"));
 

Im not sure I follow your response - it doesnt show any array slicing, just array aggregates?
 

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