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  1. #1
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    VHDL - Unknown identify

    Hello all,

    I could explicitly code the values I want but I was hoping to use attributes

    Code VHDL - [expand]
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    -- The CID register
        -- DeviCe IDentification register.
        --     Stores information about device
        type cid_reg_t is
            record
            mid : byte_t;                       -- Manufacture ID    
            cbx : std_logic_vector(1 downto 0); -- Device/BGA   
            oid : byte_t;                       -- OEM/Application ID 
            pnm : word48_t;                     -- Product Name 
            prv : byte_T;                       -- Product Revision
            psn : dword_t;                      -- Product Serial number
            mdt : byte_t;                       -- Manufacturing Date
            crc : word7_t;                      -- CRC
        end record;
        
        constant cid_reg_rst_t : cid_reg_t := (
        mid => (others => '0'), cbx => (others => '0'), oid => (others => '0'), 
        pnm => (others => '0'), prv => (others => '0'), psn => (others => '0'),
        mdt => (others => '0'), crc => (others => '0'));
     
        constant cid_reg_w100_default : cid_reg_t := (
            mid => std_logic_vector(
                            to_unsigned(
                            16#70#, mid'length),
            cbx => std_logic_vector(to_unsigned(16#1#,cbx'length),
            oid => std_logic_vector(to_unsigned(16#0#,oid'length), 
            pnm => std_logic_vector(to_unsigned(16#5731303332#,pnm'length), -- W10032
            prv => std_logic_vector(to_unsigned(16#B9#,prv'length),
            psn => std_logic_vector(to_unsigned(16#A60366#,psn'length),
            mdt => std_logic_vector(to_unsigned(16#12#,mdt'length),
            crc => std_logic_vector(to_unsigned(16#5E#,crc'length));

    Code:
    # ** Error: ../tbench/eMMC/emmc_pkg.vhd(242): (vcom-1136) Unknown identifier "mid".
    # ** Error: ../tbench/eMMC/emmc_pkg.vhd(242): Prefix of attribute "length" must be appropriate for an array object or must denote an array subtype.
    Where line 242 is refering to the mid'length bit.

    I know I can get rid of this error by doing
    Code VHDL - [expand]
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    16#70#, cid_reg_rst_t.mid'length),
    However this requires I have already declared a signal beforehand. Does anyone know of a way I can use the current signal that I'm trying to code up, or the record type? For example if constant cid_Reg_rst_t didn't exist yet.

    Regards,
    Wes

    •   Alt30th October 2017, 12:13

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  2. #2
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    Re: VHDL - Unknown identify

    You can use the type directly, as you can use all of the array attributes on an object(signal/variable/constant) or on a type.

    to_unsigned(16#70#, byte_t'length);

    I do find it odd though, that you're converting all the integers to SLV, when you are writing all of the literals in Hex. Why not just write them in normal hex array form

    mid => x"70";

    For anything that is not divisible by 4 bits, if you can use a 2008 compiler, you can use new format identifiers.

    my_7bit_array => 7x"70"; -- 1110000



    •   Alt30th October 2017, 12:26

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  3. #3
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    Re: VHDL - Unknown identify

    I have sections which are not divisible by 4 bits and unfortunately we're trying to achieve do254, for some reason the higher ups don't believe we should be using 2008. Thus the integer conversion method.

    However something you said about literals made me recall - peter ashenden - designer guide, where is states under lexical elements, how one uses bit string literals
    Furthermore looking at standard

    bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] ".

    Given this do you ever do conversions like to_unsigned(16#70#, x'length)

    Or do you do the following

    [x'length]D"70";

    ??

    ------------------
    # ** Error: near "D": Decimal bit string literals not supported for this language version.
    # ** Error: Length field for bit string literal is not defined until VHDL 2008.
    Last edited by wesleytaylor; 30th October 2017 at 14:37.



    •   Alt30th October 2017, 14:17

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  4. #4
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    Re: VHDL - Unknown identify

    I have used to_unsigned(16#70#, x'length) in the past, for exact same reasons you are (keeping 1993 compliant)
    But you cannot do the 2nd option - when specifying literals, the length must also be a literal, so you cannot use an attribute to create the correct length. Its basically copied from verilog thats been able to do it for years.

    Personally, Ill go with whatever is easiest for someone else to understand. A length field Ill probably specify as a decimal integer, while an address or data can probably remain as hex.



  5. #5
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    Re: VHDL - Unknown identify

    Quote Originally Posted by wesleytaylor View Post
    We're trying to achieve do254, for some reason the higher ups don't believe we should be using 2008. Thus the integer conversion method.
    Sounds like your higher ups don't understand DO-254.



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