kcounter loop filter

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/27/2017 12:01:45 AM
-- Design Name: 
-- Module Name: pfd1 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pfd1 is
    Port ( 
           A : in STD_LOGIC;
           ref : in STD_LOGIC;
           div : in STD_LOGIC;
           UP : out STD_LOGIC;
           DOWN : out STD_LOGIC);
end pfd1;

architecture Behavioral of pfd1 is

signal up1 , down1 , reset :std_logic;

component dff is
    Port ( 
           D : in STD_LOGIC;
           clk : in STD_LOGIC;
           sync_reset : in STD_LOGIC;
           Q : out STD_LOGIC);
           
end component;           

begin
   
   D1 : dff
        port map
              (
                D => A,
                clk => ref,
                sync_reset => reset,
                Q => up1
                );
                
                
   D2 : dff
                       port map
                             (
                               D => A,
                               clk => div,
                               sync_reset => reset,
                               Q => down1
                               );  
                               
                      reset <= up1 and down1;
                      UP <= up1;
                      DOWN <= down1;            
end Behavioral;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;



ENTITY loop_filter IS
-- Declarations
 port (	CLK		: in std_logic;
			RESET	: in std_logic;
			C			: in signed(7 downto 0);
			D1		: out signed(11 downto 0);
			D2		: out signed(11 downto 0)
		);
END loop_filter  ;


ARCHITECTURE behavior OF loop_filter  IS

signal E : signed(11 downto 0);
signal dtemp : signed(11 downto 0);

begin
process(CLK, RESET)
begin
        if (RESET='1') then
            D1 <= (others => '0');
						D2 <= (others => '0');
						E <= (others => '0');
						dtemp <= (others => '0');
        elsif rising_edge(CLK) then
						dtemp <=  (C(7)&C(7)&C(7)&C&'0') + dtemp - E;
						E <= dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11)&dtemp(11 downto 4);
						D1 <= dtemp; 
						D2 <= dtemp(11 downto 4)&"0000";
	  end if;
end process;
END behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- the value of k is 8

   
entity updown is
    Port ( clk: in std_logic; -- clock input
           reset: in std_logic; -- reset input 
     up_down: in std_logic; -- up or down
           carry: out std_logic;
           borrow: out std_logic 
     );
end updown;

architecture Behavioral of updown is
signal counter_up: std_logic_vector(3 downto 0);
signal counter_down: std_logic_vector(3 downto 0);
begin
-- down counter
process(clk,reset)
begin
if(rising_edge(clk)) then
    if(reset='1'or counter_up="1000") then
         counter_up <= x"0";
         end if;
         
         if(reset='1'or counter_down="1000") then
         counter_down <= x"0";
    elsif(up_down='1') then
         counter_down <= counter_down + x"1"; -- count 
  else 
   counter_up <= counter_up + x"1"; -- count up
    end if;
 end if;
 if(counter_up > "100") then
 carry <='1';
 else
 carry <='0';
 end if;
 if(counter_down > "100") then
  borrow <='1';
  else
  borrow <='1';
  end if;
end process;


end Behavioral;

if(counter_down > "100") then
  borrow <='1';
  else
  borrow <='1';
  end if;