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How to write a rising-edge D flip flop program using a Verilog

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smeschke

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here is what I have but it keeps failing:

Code Verilog - [expand]
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module DFF(clock,D,Q,Qbar);
  input clock, D;
  output reg Q; 
always block
    output Qbar;
    assign Qbar = ~ Q; 
    always @(posedge clock) 
      Q = D;
endmodule


Any ideas?
 
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Re: how to write a rising-edge D flip flop program using a Verilog

Hi,

but it keeps failing:
Click to expand...
...means what?

Klaus
 

Re: how to write a rising-edge D flip flop program using a Verilog

Oops, forgot to post the output:

testbench.sv:7: syntax error
testbench.sv:7: error: malformed statement
testbench.sv:8: warning: implicit definition of wire 'Qbar'.
Exit code expected: 0, received: 1
Click to expand...
Done
 
Last edited by a moderator:

Re: how to write a rising-edge D flip flop program using a Verilog

I found it - I had accidentally added something from a comment block in as code and that is what the issue was. I removed it and then it complied successfully.

Code Verilog - [expand]
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always block
 

Re: how to write a rising-edge D flip flop program using a Verilog

smeschke said:
I found it - I had accidentally added something from a comment block in as code and that is what the issue was. I removed it and then it complied successfully.

Code Verilog - [expand]
1

always block
Click to expand...

that's good. but... now think about the task at hand. describing a flip-flop module is not what RTL is supposed to be used for. you want to write code that will infer a flop. it's a subtle but important difference.
 

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