Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Concatenation problem in port map in vhdl

Status
Not open for further replies.

moonshine8995

Newbie level 6
Joined
Aug 4, 2017
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
150
Concatination problem in port map in vhdl

i want to port map
Code:
out_x=> mid
out is 32 bit std_logic_vector and mid is 16 bit std_logic_vector.
how should i do this?
i change it to this
Code:
out  => (x"0000" &mid)
but i see this error
Code:
Formal "out_x" of mode OUT cannot be associated with an expression.
thanks.
 

Re: concatination problem in port map in vhdl

Out(15 downtown 0) => mid;
 

Re: concatination problem in port map in vhdl

the out and mid size shouldn't be changed!
 

Re: concatination problem in port map in vhdl

the out and mid size shouldn't be changed!

I dont get what you're talking about, I didnt change any sizes, I just assigned the 16 LSBs of out to mid. You can assign the 16 MSbs to whatever you want:

Code:
out(31 downto 16) => x"0000",
Out(15 downto 0) => mid,
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top