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Simulation guideline of RTL and Netlist mixed simulation

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How to avoid race condition on RTL and Netlist mixed simulation

Hi,

Currently we have met some race conditions when doing RTL + Netlist simulation using irun, where RTL is the top module and some blocks are Netlist.
We tried +delay_mode_unit and +delay_mode_zero option, and still fails.

Whether there're guidelines for this kind of simulation, eg. how to avoiding race conditions in-between RTL and Netlist block interface ?

ps.
The below thread has the similar title but not state the same thing.
https://www.edaboard.com/showthread.php?t=266399


Thanks for your help.
Martin
 

Can you clarify what race conditions you are seeing? Several issues in GLS are due to setup/hold violations. Your RTL will generate new data in zero time, violating the flop hold values on the gate level modules. You have to fake delays in some way.
 

ThisIsNotSam said:
Can you clarify what race conditions you are seeing? Several issues in GLS are due to setup/hold violations. Your RTL will generate new data in zero time, violating the flop hold values on the gate level modules. You have to fake delays in some way.
Click to expand...

Sorry I wasn't describe the situation clearly enough.
1. we're just trying the pre-sim with no_timing_check and no_specify options, so the simulator won't check setup/hold violations
2. I have lost the wave and logic with the race condition. do you mean we have to manually add fake delays in the problematic rtl, once we hit race condition ? or there are sim options could solve it in a more general way ? for a no_timing_check simulation

thank you
 

There are issues with the no_timing_check depending on how the std cell library gate level verilog is described. You might make the setup/hold warning messages disappear, but the Xs are still there. I know I have had that issue before, it's worth checking.

What I meant about fake delays is that you can try to purposefully make your RTL simulation work on the opposite edge as the gate level simulation, this should prevent all the hold issues. Then you are only left with setup.
 

Thanks for the tip on the opposite edge for rtl, we'll try it.

for the std lib, we've add some #delay to the flop cells, and it works on the pure netlist sim with +delay_mode_unit option
 

Inverting the clock solves the hold time issue on the RTL --> gates signals by providing 1/2 cycle of hold time. You need to be careful that your logic is fast enough to still meet the setup time with that late of input signal.

You also have a problem on the gates -> RTL signals in that the gates must now provide 1/2 clock of hold time. You will have some hold time but probably not enough to prevent "Shoot Through" on those signals.

John Eaton
 

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