+ Post New Thread
Results 1 to 15 of 15
  1. #1
    Member level 4
    Points: 1,254, Level: 8

    Join Date
    Oct 2012
    Posts
    68
    Helped
    0 / 0
    Points
    1,254
    Level
    8

    Unable to interface a VGA screen with a FPGA development board

    Hi,

    I was trying to interface a monitor (HP L1506) with an FPGA development board using the Pong P. Chu’s code available here (ch 12; vga_syn.vhd and vga_syn_test.vhd) with a clk of 25 MHz. On doing so the screen displayed a message ‘Input signal out of range. Change settings to 1024X768 – 60 Hz’. When I checked the manual of the monitor (available here), page B-6 listed the VGA resolution as a preset mode which is to be detected automatically. So why am I not getting any display on the screen (when I asserted the reset; the message changed to ‘check display cable’; ie. there is communication between the FPGA development board and the monitor). The development board has 1 pin assigned per colour channel.

    Am I doing anything wrong / skipping something? Pls. advise.


    Thanking You,

    Arvind Gupta
    Last edited by garvind25; 27th October 2017 at 10:38.

    •   Alt27th October 2017, 10:29

      advertising

        
       

  2. #2
    Super Moderator
    Points: 51,995, Level: 55
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster

    Join Date
    Apr 2014
    Posts
    10,442
    Helped
    2485 / 2485
    Points
    51,995
    Level
    55

    Re: Unable to interface a VGA screen with a FPGA development board

    Hi,

    Am I doing anything wrong
    How can we answer this without seeing what you have done?

    --> show us your schematic, your code and your setup.

    Klaus



  3. #3
    Member level 4
    Points: 1,254, Level: 8

    Join Date
    Oct 2012
    Posts
    68
    Helped
    0 / 0
    Points
    1,254
    Level
    8

    Re: Unable to interface a VGA screen with a FPGA development board

    OK. There is no schematic of the board (its from a local vendor ; if that is what you meant by schematic). The codes are as below (download link and the files were mentioned above):

    === Code ====

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity vga_sync is
       port(
          clk, reset: in std_logic;
          hsync, vsync: out std_logic;
          video_on, p_tick: out std_logic;
          pixel_x, pixel_y: out std_logic_vector (9 downto 0)
        );
    end vga_sync;
    
    architecture arch of vga_sync is
       -- VGA 640-by-480 sync parameters
       constant HD: integer:=640; --horizontal display area
       constant HF: integer:=16 ; --h. front porch
       constant HB: integer:=48 ; --h. back porch
       constant HR: integer:=96 ; --h. retrace
       constant VD: integer:=480; --vertical display area
       constant VF: integer:=10;  --v. front porch
       constant VB: integer:=33;  --v. back porch
       constant VR: integer:=2;   --v. retrace
       -- mod-2 counter
       signal mod2_reg, mod2_next: std_logic;
       -- sync counters
       signal v_count_reg, v_count_next: unsigned(9 downto 0);
       signal h_count_reg, h_count_next: unsigned(9 downto 0);
       -- output buffer
       signal v_sync_reg, h_sync_reg: std_logic;
       signal v_sync_next, h_sync_next: std_logic;
       -- status signal
       signal h_end, v_end, pixel_tick: std_logic;
    begin
       -- registers
       process (clk,reset)
       begin
          if reset='1' then
             mod2_reg <= '0';
             v_count_reg <= (others=>'0');
             h_count_reg <= (others=>'0');
             v_sync_reg <= '0';
             h_sync_reg <= '0';
          elsif (clk'event and clk='1') then
             mod2_reg <= mod2_next;
             v_count_reg <= v_count_next;
             h_count_reg <= h_count_next;
             v_sync_reg <= v_sync_next;
             h_sync_reg <= h_sync_next;
          end if;
       end process;
       -- mod-2 circuit to generate 25 MHz enable tick
       mod2_next <= not mod2_reg;
       -- 25 MHz pixel tick
       pixel_tick <= '1' when mod2_reg='1' else '0';
       -- status
       h_end <=  -- end of horizontal counter
          '1' when h_count_reg=(HD+HF+HB+HR-1) else --799
          '0';
       v_end <=  -- end of vertical counter
          '1' when v_count_reg=(VD+VF+VB+VR-1) else --524
          '0';
       -- mod-800 horizontal sync counter
       process (h_count_reg,h_end,pixel_tick)
       begin
          if pixel_tick='1' then  -- 25 MHz tick
             if h_end='1' then
                h_count_next <= (others=>'0');
             else
                h_count_next <= h_count_reg + 1;
             end if;
          else
             h_count_next <= h_count_reg;
          end if;
       end process;
       -- mod-525 vertical sync counter
       process (v_count_reg,h_end,v_end,pixel_tick)
       begin
          if pixel_tick='1' and h_end='1' then
             if (v_end='1') then
                v_count_next <= (others=>'0');
             else
                v_count_next <= v_count_reg + 1;
             end if;
          else
             v_count_next <= v_count_reg;
          end if;
       end process;
       -- horizontal and vertical sync, buffered to avoid glitch
       h_sync_next <=
          '1' when (h_count_reg>=(HD+HF))           --656
               and (h_count_reg<=(HD+HF+HR-1)) else --751
          '0';
       v_sync_next <=
          '1' when (v_count_reg>=(VD+VF))           --490
               and (v_count_reg<=(VD+VF+VR-1)) else --491
          '0';
       -- video on/off
       video_on <=
          '1' when (h_count_reg<HD) and (v_count_reg<VD) else
          '0';
       -- output signal
       hsync <= h_sync_reg;
       vsync <= v_sync_reg;
       pixel_x <= std_logic_vector(h_count_reg);
       pixel_y <= std_logic_vector(v_count_reg);
       p_tick <= pixel_tick;
    end arch;
    =====

    ===Testbench===

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    entity vga_test is
       port (
          clk, reset: in std_logic;
          sw: in std_logic_vector(2 downto 0);
          hsync, vsync: out  std_logic;
          rgb: out std_logic_vector(2 downto 0)
       );
    end vga_test;
    
    architecture arch of vga_test is
       signal rgb_reg: std_logic_vector(2 downto 0);
       signal video_on: std_logic;
    begin
       -- instantiate VGA sync circuit
       vga_sync_unit: entity work.vga_sync
          port map(clk=>clk, reset=>reset, hsync=>hsync,
                   vsync=>vsync, video_on=>video_on,
                   p_tick=>open, pixel_x=>open, pixel_y=>open);
       -- rgb buffer
       process (clk,reset)
       begin
          if reset='1' then
             rgb_reg <= (others=>'0');
          elsif (clk'event and clk='1') then
             rgb_reg <= sw;
          end if;
       end process;
       rgb <= rgb_reg when video_on='1' else "000";
    end arch;
    =====

    'sw' in test bench is to be assigned to switches. Depending on the values of sw, red, green, blue etc colours are to be displayed over the entire screen.

    Regards,
    Arvind Gupta
    Last edited by KlausST; 27th October 2017 at 12:28. Reason: added code tags



  4. #4
    Super Moderator
    Points: 51,995, Level: 55
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster

    Join Date
    Apr 2014
    Posts
    10,442
    Helped
    2485 / 2485
    Points
    51,995
    Level
    55

    Re: Unable to interface a VGA screen with a FPGA development board

    Hi,

    Without schematic you can´t assign the signal to the correct pad.
    Still the setup is missing, like I/O, or what type of FPGA you are using, supply voltages and so on.

    I´ll come back when the informations are complete.

    Klaus



    •   Alt27th October 2017, 12:31

      advertising

        
       

  5. #5
    Full Member level 1
    Points: 1,820, Level: 9
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    115
    Helped
    10 / 10
    Points
    1,820
    Level
    9

    Re: Unable to interface a VGA screen with a FPGA development board

    You are leaving out a lot of information that would be extremely helpful in troubleshooting your problem. Consider providing some information about the circuit board, FPGA, and the constraints you are using.

    Couple questions: are you sure the output signals are mapped to the correct FPGA pins in your constraints file? Have you tried taking an oscilloscope to some of the pins and verifying the signals are what you would expect?

    I took a look at the code, it's not great but it should work. I would suggest adding a register to the video on signal in vga_sync.vhd. The changes I made to your code are in bold.

    Code:
    architecture arch of vga_sync is
        -- VGA 640-by-480 sync parameters
        constant HD                        : integer := 640;  --horizontal display area
        constant HF                        : integer := 16;   --h. front porch
        constant HB                        : integer := 48;   --h. back porch
        constant hr                        : integer := 96;   --h. retrace
        constant VD                        : integer := 480;  --vertical display area
        constant VF                        : integer := 10;   --v. front porch
        constant VB                        : integer := 33;   --v. back porch
        constant VR                        : integer := 2;    --v. retrace
        -- mod-2 counter
        signal mod2_reg, mod2_next         : std_logic;
        -- sync counters
        signal v_count_reg, v_count_next   : unsigned(9 downto 0);
        signal h_count_reg, h_count_next   : unsigned(9 downto 0);
        -- output buffer
        signal v_sync_reg, h_sync_reg      : std_logic;
        signal v_sync_next, h_sync_next    : std_logic;
        signal video_on_reg, video_on_next : std_logic;
        -- status signal
        signal h_end, v_end, pixel_tick    : std_logic;
    
    begin
        -- registers
        process (clk, reset)
        begin
            if reset = '1' then
                mod2_reg     <= '0';
                v_count_reg  <= (others => '0');
                h_count_reg  <= (others => '0');
                v_sync_reg   <= '0';
                h_sync_reg   <= '0';
                video_on_reg <= '0';
            elsif (clk'event and clk = '1') then
                mod2_reg     <= mod2_next;
                v_count_reg  <= v_count_next;
                h_count_reg  <= h_count_next;
                v_sync_reg   <= v_sync_next;
                h_sync_reg   <= h_sync_next;
                video_on_reg <= video_on_next;
            end if;
        end process;
        -- mod-2 circuit to generate 25 MHz enable tick
        mod2_next  <= not mod2_reg;
        -- 25 MHz pixel tick
        pixel_tick <= '1' when mod2_reg = '1' else '0';
        -- status
        h_end <= '1' when h_count_reg = (HD+HF+HB+hr-1) else  --799
                 '0'; 
        v_end <= '1' when v_count_reg = (VD+VF+VB+VR-1) else  --524
                 '0';
        -- mod-800 horizontal sync counter
        process (h_count_reg, h_end, pixel_tick)
        begin
            if pixel_tick = '1' then        -- 25 MHz tick
                if h_end = '1' then
                    h_count_next <= (others => '0');
                else
                    h_count_next <= h_count_reg + 1;
                end if;
            else
                h_count_next <= h_count_reg;
            end if;
        end process;
        -- mod-525 vertical sync counter
        process (v_count_reg, h_end, v_end, pixel_tick)
        begin
            if pixel_tick = '1' and h_end = '1' then
                if (v_end = '1') then
                    v_count_next <= (others => '0');
                else
                    v_count_next <= v_count_reg + 1;
                end if;
            else
                v_count_next <= v_count_reg;
            end if;
        end process;
        -- horizontal and vertical sync, buffered to avoid glitch
        h_sync_next <= '1' when (h_count_reg >= (HD+HF))  --656
    and (h_count_reg <= (HD+HF+hr-1)) else  --751
                       '0';
        v_sync_next <= '1' when (v_count_reg >= (VD+VF))  --490
    and (v_count_reg <= (VD+VF+VR-1)) else  --491
                       '0';
        -- video on/off
        video_on_next <= '1' when (h_count_reg < HD) and (v_count_reg < VD) else
                         '0';
        -- output signal
        hsync    <= h_sync_reg;
        vsync    <= v_sync_reg;
        video_on <= video_on_reg;
        pixel_x  <= std_logic_vector(h_count_reg);
        pixel_y  <= std_logic_vector(v_count_reg);
        p_tick   <= pixel_tick;
    end arch;



  6. #6
    Member level 4
    Points: 1,254, Level: 8

    Join Date
    Oct 2012
    Posts
    68
    Helped
    0 / 0
    Points
    1,254
    Level
    8

    Re: Unable to interface a VGA screen with a FPGA development board

    OK...the FPGA vendor gave me a pin connection list only ie. for LED1 pin no 16, for LED 2 pin no. 18 and so on. There is no schematic. The board has LED indicators for supply to FPGA; VCCO = 3.3v, VCCINT = 2.5v and VCC = 5v (I guess this is for LCD display). The board has XC3S400 IC (PQ208 packaging). I cross checked the ucf file; the pin assignment is OK. BTW in ISE 10.1, like for CPLDs where I can select which I/O voltage levels to use (LVCMOS 18/ LVCMOS33 etc), is that done in case of Spartan 3 FPGAs also. If so, where is the option pls? I could not find it in any of the property options at processes window of ISE.

    Thanks and Regards,
    Arvind Gupta

    - - - Updated - - -

    Also can anyone kindly look at the test circuit code. As I know a component is first declared before beginning architecture and then port mapped inside the architecture.

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    entity vga_test is
       port (
          clk, reset: in std_logic;
          sw: in std_logic_vector(2 downto 0);
          hsync, vsync: out  std_logic;
          rgb: out std_logic_vector(2 downto 0)
       );
    end vga_test;
    
    architecture arch of vga_test is
       signal rgb_reg: std_logic_vector(2 downto 0);
       signal video_on: std_logic;
    begin
       -- instantiate VGA sync circuit
       vga_sync_unit: entity work.vga_sync
          port map(clk=>clk, reset=>reset, hsync=>hsync,
                   vsync=>vsync, video_on=>video_on,
                   p_tick=>open, pixel_x=>open, pixel_y=>open);
       -- rgb buffer
       process (clk,reset)
       begin
          if reset='1' then
             rgb_reg <= (others=>'0');
          elsif (clk'event and clk='1') then
             rgb_reg <= sw;
          end if;
       end process;
       rgb <= rgb_reg when video_on='1' else "000";
    end arch;
    Here there is no component declaration done, only port mapping of the DUT has been done. The sixth line from top (in architecture) has an entity declaration, whereas this test circuit code already has an entity declaration.

    Thanks,
    Arvind Gupta
    Last edited by garvind25; 1st November 2017 at 11:38.



  7. #7
    Full Member level 3
    Points: 1,545, Level: 8

    Join Date
    May 2014
    Posts
    182
    Helped
    18 / 18
    Points
    1,545
    Level
    8

    Re: Unable to interface a VGA screen with a FPGA development board

    Arvind,

    When designing/debugging you should follow this rough guideline.

    1. See you hdl files simulate & are synthesisable
    2. Hardware setup check.
    a. Make sure you're hardware/schematic doesn't require any additional signal to turn on buffers etc. (given it's a Spartan dev board you should get some info regarding board configuration)
    b. Make sure your pin list is mapped to your fpga.
    c. Scope your outputs. Ensure that your fpga is outputting what you hope for.
    3. Check your external device characteristics.
    a. Sometimes external devices don't "just work" they require a dance of initialisation before they come to life.
    4. Profit.

    Out of these 4 points where do you think you're up to?

    I guess you're parroting chapter 12 of FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version.
    Do you have the same hardware?



    •   Alt1st November 2017, 14:33

      advertising

        
       

  8. #8
    Full Member level 1
    Points: 1,820, Level: 9
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    115
    Helped
    10 / 10
    Points
    1,820
    Level
    9

    Re: Unable to interface a VGA screen with a FPGA development board

    wesleytaylor provided some good guidelines to follow.

    I have a few questions:
    What is the clock frequency going into the FPGA? The clock input requires a 50 MHz signal for the design to work... is it 50 MHz? Any reason you wouldn't post up the UCF file? How about a picture of the board at least. Do you have a digital camera?

    This is a crap shoot unless you provide more information about your board. Like who made it? ...does it have a part number? ...did it come with any files? ...where did you buy it from?



  9. #9
    Member level 4
    Points: 1,254, Level: 8

    Join Date
    Oct 2012
    Posts
    68
    Helped
    0 / 0
    Points
    1,254
    Level
    8

    Re: Unable to interface a VGA screen with a FPGA development board

    OK... my kit has a 25 MHz crystal oscillator. So maybe that is where the error is. Posting the ucf file as below (posting it as a code as I dont see the option for attaching a file with the post). I just want to check if the VGA port works on the board. (I got this board from a friend; he dosnt have the file /CDs etc). Do you have any code which will simply check the VGA interface of this board? I repeat, it a locally made board; no manufacturer, no part number etc. And yes, I dont have a digital camera...

    Code:
     
    
    
    #PACE: Start of Constraints generated by PACE
    
    #PACE: Start of PACE I/O Pin Assignments
    NET "clk"  LOC = "p180"  ;
    NET "hsync"  LOC = "p108"  ;
    NET "reset"  LOC = "p101"  ;
    NET "rgb<0>"  LOC = "p109"  ;
    NET "rgb<1>"  LOC = "p111"  ;
    NET "rgb<2>"  LOC = "p113"  ;
    NET "sw<0>"  LOC = "p76"  ;
    NET "sw<1>"  LOC = "p77"  ;
    NET "sw<2>"  LOC = "p78"  ;
    NET "vsync"  LOC = "p107"  ;
    
    #PACE: Start of PACE Area Constraints
    
    #PACE: Start of PACE Prohibit Constraints
    
    #PACE: End of Constraints generated by PACE
    Thanks and Regards,
    Arvind Gupta



  10. #10
    Advanced Member level 3
    Points: 4,655, Level: 16

    Join Date
    Dec 2015
    Location
    Madrid, Spain
    Posts
    816
    Helped
    200 / 200
    Points
    4,655
    Level
    16

    Re: Unable to interface a VGA screen with a FPGA development board

    The following code is the one I used to check whether or not the VGA port works and to adjust the porches.
    This code worked on a VGA 640x480. I took porches values from the guide of the board and adjusted them with this code via experimentation.

    As you can see, my FPGA had a 50 MHz clock, but, you do not need a 50 MHz clock for a 640x480 resolution, instead you need close to 25 MHz for a 60 Hz refresh rate of the screen (800 pixels*521 lines*1/(25*10^6)=1/60 which will be the refresh rate). As you can see, the first thing I did was to divide the clock down via a simple clock divider (later on, I placed it in a separate component.. this code was just the first test).

    If you have 25 MHz clock, just erase the clock divider process, erase the signal "clk25" and rename the "clk" in the entity with "clk25" and you are set to go.

    As you can see in the last line of the code, this code will make a red screen.

    Last thing, comments are in Spanish, so use a translator if you want to understand them.. even though you can just run the code without understanding anything.


    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    69
    70
    71
    72
    73
    74
    75
    76
    77
    78
    79
    80
    81
    82
    83
    84
    85
    86
    87
    88
    
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
     
    ----------------------
    entity vga640x480 is
     
    port (
        clk,clr:    in std_logic; --input 50 MHz clock and clear
        hsync:      out std_logic; --horizontal sync pulse
        vsync:      out std_logic; --vertical sync pulse
        rgb:        out std_logic_vector(2 downto 0)-- red,green,blue
        );
        
    end vga640x480;
    --------
    architecture Behavioral of vga640x480 is
     
    constant hpixels: integer :=800; --nº pixeles horizontales (horizontal pixels)
    constant vlines:    integer :=521; --nº de lineas horizontales (vertical lines)
     
    constant HFP:       integer :=16; --horizontal front porch
    constant HBP:       integer :=48; --horizontal back porch
    constant HSP:       integer :=96; --horizontal sync pulse duration in pixels
    constant HVA:       integer :=640;--horizontal visible area i.e. visible horizontal pixels per horizontal line 
     
    constant VFP:       integer :=10; --vertical front porch
    constant VBP:       integer :=29; --vertical back porch
    constant VSP:       integer :=2;  --vertical sync pulse duration in pixels
    constant VVA:       integer :=480;--vertical visible area
     
    signal hCounter,vCounter: unsigned(9 downto 0); --Contadores que llevan la cuenta de los pixeles en los que estoy
    signal displayON:   std_logic;--activacion del display i.e. si se puede escribir pixeles o NO
    signal hEND : std_logic;--fin linea horizontal
    signal clk25: std_logic;--25 MHz clock
     
    begin
     
    --Clock frequency divider (PONERLO EN COMPONENTE SEPARADO)
    process(clk,clr)
        begin
        if clr ='1' then
            clk25 <='0';
        elsif rising_edge(clk) then
                clk25 <= not clk25;
        end if;
        end process;
     
    --Contar pixeles horizontales
    process(clk25,clr)
        begin
            if clr='1' then
                hCounter <= (others => '0'); --parte asíncrona, reseteas contadores
                elsif (clk25'event and clk25 = '1') then --ver si clk_locked esta locked se ha incluido en el "clr"
                    if hCounter=to_unsigned(hpixels-1,hCounter'length) then --has llegado al final de la linea horizontal
                        hCounter <= (others => '0') ; --reset contador
                        hEND <='1';
                    else
                        hCounter <= hCounter+1; --incrementas contador
                        hEND <='0';
                    end if;
            end if;
        end process;
     
    --Contar lineas horizontales dibujadas
    process(clk25,clr)
        begin
            if clr='1' then
                vCounter <= (others => '0');
                elsif (clk25'event and clk25 = '1' and hEND = '1') then
                    if vCounter=to_unsigned(vlines-1,vCounter'length) then --has dibujado la ultima linea horizontal
                        vCounter <= (others => '0');--reset contador vertical
                    else
                        vCounter <= vCounter+1; -- incremento contador de lineas dibujadas en horizontal
                    end if;
            end if;
        end process;
        
    hsync <= '0' when ((hCounter >= HVA+HBP) and (hCounter < HVA+HBP+HSP)) else '1' ; --lo pones a 0 cuando contador horizontal está entre 0 y 95
    vsync <= '0' when ((vCounter >= VVA+VBP) and (vCounter < VVA+VBP+VSP)) else '1' ; -- lo pones a 0 cuando contador vertical está entre 0 y 1
     
    --Condicion de que se pueda dibujar pixeles en el display (pantalla)
     
    displayON <= '1' when ((hCounter < HVA) and (vCounter < VVA)) else '0';
     
    rgb <= "100" when displayON='1' else "000";
     
    end Behavioral;


    1 members found this post helpful.

  11. #11
    Member level 4
    Points: 1,254, Level: 8

    Join Date
    Oct 2012
    Posts
    68
    Helped
    0 / 0
    Points
    1,254
    Level
    8

    Re: Unable to interface a VGA screen with a FPGA development board

    Thanks for the code I was able to run it. Initially when I ran it as it is, there was no output on screen. Next, when I changed the value at line 20 to 600 for 25 Mhz clock and 50 Hz refresh rate, I got a thin line near the top of the screen fading downwards up to a few inches ie I got some display. When I toggled with the value of rgb to ‘010’, ‘001’ etc I got the various colours. So basically the hardware is communicating with the display. If you have some time to spare then one more thing pls. – is there a way to get the entire screen as red, green, blue etc? Presently I am getting only a thin line fading downwards upto a few inches.

    Thanks again,
    Arvind Gupta



  12. #12
    Advanced Member level 3
    Points: 4,655, Level: 16

    Join Date
    Dec 2015
    Location
    Madrid, Spain
    Posts
    816
    Helped
    200 / 200
    Points
    4,655
    Level
    16

    Re: Unable to interface a VGA screen with a FPGA development board

    Quote Originally Posted by garvind25 View Post
    Presently I am getting only a thin line fading downwards upto a few inches.
    Then it is not working as it should. The code I showed must make the entire screen red, not just a line.
    Are you sure you have connected correctly before synthesizing the VGA pins to the FPGA (R,G,B,hSync,vSync) ?

    If you want to do other things with the VGA, the whole trick is using the "hCounter" (horizontal counter) and "vCounter" (vertical counter). Those are the ones saying where you are. Imagine the A4 paper is your screen. The top left corner is the (0,0) position. The hCounter is the horizontal axis and vCounter is the vertical axis.
    When those counters arrive to the bottom right side of the A4 paper (screen), i.e. at the point (799,520), they are reset, which means, in the next clock tick, you are again at the top left side of the A4 paper (screen).
    Another thing is to know that you can not write in all pixels... only in the visible area which has 640x480 pixels.
    In the code shown, I have made the wild assumption saying that the visible area starts right at (0,0) and ends at (639,479), but who says that it will be like that in reality ? What if the visible area starts at (20,30) and ends at (20+640,30+480)=(660,510) ? This is what I was saying that you need to adjust the "porches" so that you make the visible area fit the screen perfectly, the code shown helps you do that. (see picture)
    I am NOT saying that you need to increment/decrement porches length, you always have to sum up 800 and 521 generally (I remember that the particular screen I worked with, needed to go to 800 and 525). I am saying that you need to replace where the front porches/back porch starts ... for example it could be:
    Front porch --> horizontal/vertical display --> back porch --> synch pulse. You have to play with the place of those 4 things.


    If you want to set a particular pixel at a given color, just set that color when the counters are at that particular position like this:
    Code VHDL - [expand]
    1
    
    rgb <= "111" when displayON='1' and hCounter=xx and vCounter=yy else "000";
    Last edited by CataM; 3rd November 2017 at 14:34.



    •   Alt3rd November 2017, 14:08

      advertising

        
       

  13. #13
    Full Member level 1
    Points: 1,820, Level: 9
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    115
    Helped
    10 / 10
    Points
    1,820
    Level
    9

    Re: Unable to interface a VGA screen with a FPGA development board

    Since the oscillator is 25 MHz you will need to make some changes to the original code since it was created for a different development board. The mod2 signals will need to be deleted to remove the clock divider. The pix_tick enable signals should be deleted as well.



  14. #14
    Member level 4
    Points: 1,254, Level: 8

    Join Date
    Oct 2012
    Posts
    68
    Helped
    0 / 0
    Points
    1,254
    Level
    8

    Re: Unable to interface a VGA screen with a FPGA development board

    Quote Originally Posted by BlackHelicopter View Post
    The pix_tick enable signals should be deleted as well.
    I was referring to the code in post #10. If you were referring to the same, pls. indicate the line number(s). I could not find pix_tick enable signal in the code.

    Regards,
    Arvind Gupta



  15. #15
    Full Member level 1
    Points: 1,820, Level: 9
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    115
    Helped
    10 / 10
    Points
    1,820
    Level
    9

    Re: Unable to interface a VGA screen with a FPGA development board

    Here's the new vga_sync
    Code VHDL - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    69
    70
    71
    72
    73
    74
    75
    76
    77
    78
    79
    80
    81
    82
    83
    84
    85
    86
    87
    88
    89
    90
    91
    92
    93
    94
    95
    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity vga_sync is
        port(
            clk, reset       : in  std_logic;
            hsync, vsync     : out std_logic;
            video_on, p_tick : out std_logic;
            pixel_x, pixel_y : out std_logic_vector (9 downto 0)
            );
    end vga_sync;
     
    architecture arch of vga_sync is
        -- VGA 640-by-480 sync parameters
        constant HD                        : integer := 640;  --horizontal display area
        constant HF                        : integer := 16;   --h. front porch
        constant HB                        : integer := 48;   --h. back porch
        constant hr                        : integer := 96;   --h. retrace
        constant VD                        : integer := 480;  --vertical display area
        constant VF                        : integer := 10;   --v. front porch
        constant VB                        : integer := 33;   --v. back porch
        constant VR                        : integer := 2;    --v. retrace
        -- sync counters
        signal v_count_reg, v_count_next   : unsigned(9 downto 0);
        signal h_count_reg, h_count_next   : unsigned(9 downto 0);
        -- output buffer
        signal v_sync_reg, h_sync_reg      : std_logic;
        signal v_sync_next, h_sync_next    : std_logic;
        signal video_on_reg, video_on_next : std_logic;
        -- status signal
        signal h_end, v_end                : std_logic;
     
    begin
        -- registers
        process (clk, reset)
        begin
            if reset = '1' then
                v_count_reg  <= (others => '0');
                h_count_reg  <= (others => '0');
                v_sync_reg   <= '0';
                h_sync_reg   <= '0';
                video_on_reg <= '0';
            elsif (clk'event and clk = '1') then
                v_count_reg  <= v_count_next;
                h_count_reg  <= h_count_next;
                v_sync_reg   <= v_sync_next;
                h_sync_reg   <= h_sync_next;
                video_on_reg <= video_on_next;
            end if;
        end process;
        -- status
        h_end <= '1' when h_count_reg = (HD+HF+HB+hr-1) else  --799
                 '0'; 
        v_end <= '1' when v_count_reg = (VD+VF+VB+VR-1) else  --524
                 '0';
        -- mod-800 horizontal sync counter
        process (h_count_reg, h_end)
        begin
                if h_end = '1' then
                    h_count_next <= (others => '0');
                else
                    h_count_next <= h_count_reg + 1;
                end if;
        end process;
        -- mod-525 vertical sync counter
        process (v_count_reg, h_end, v_end)
        begin
            if h_end = '1' then
                if (v_end = '1') then
                    v_count_next <= (others => '0');
                else
                    v_count_next <= v_count_reg + 1;
                end if;
            else
                v_count_next <= v_count_reg;
            end if;
        end process;
        -- horizontal and vertical sync, buffered to avoid glitch
        h_sync_next <= '1' when (h_count_reg >= (HD+HF))  --656
    and (h_count_reg <= (HD+HF+hr-1)) else  --751
                       '0';
        v_sync_next <= '1' when (v_count_reg >= (VD+VF))  --490
    and (v_count_reg <= (VD+VF+VR-1)) else  --491
                       '0';
        -- video on/off
        video_on_next <= '1' when (h_count_reg < HD) and (v_count_reg < VD) else
                         '0';
        -- output signal
        hsync    <= h_sync_reg;
        vsync    <= v_sync_reg;
        video_on <= video_on_reg;
        pixel_x  <= std_logic_vector(h_count_reg);
        pixel_y  <= std_logic_vector(v_count_reg);
        p_tick   <= clk;
    end arch;

    Can I ask what the point of whatever you're doing is? It's not to learn anything I gather, correct?
    Last edited by BlackHelicopter; 8th November 2017 at 03:04.



--[[ ]]--