moonshine8995
Newbie level 6
could someone help me with this code?
i want to have the output in the form of integer, but i have problem with line
which doesn't change count from std_logic_vector to out which is integer.
i see these errors
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counter IS
PORT(
clk : IN STD_LOGIC;
out_c : OUT integer
);
END counter;
architecture behav of counter is
signal count : std_logic_vector (31 downto 0) := (others => '0');
begin
counting: process (clk)
begin
if (clk'event and clk ='1') then
count <= count+ 1;
end if;
end process counting;
out_c <= to_integer(unsigned(count));
end behav;
Code:
out_c <= to_integer(unsigned(count));
i see these errors
Code:
(vcom-1078) Identifier "unsigned" is not directly visible.