Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Convert std_logic_vector to integer

Status
Not open for further replies.

moonshine8995

Newbie level 6
Joined
Aug 4, 2017
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
150
could someone help me with this code?
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;

ENTITY counter IS
PORT(
clk : IN STD_LOGIC;
out_c : OUT integer
);
END counter;

architecture behav of counter is
signal count : std_logic_vector (31 downto 0) := (others => '0');
begin
counting: process (clk)
begin
if (clk'event and clk ='1') then
			count <= count+ 1;
	end if;
end process counting;
	 out_c <= to_integer(unsigned(count));
end behav;
i want to have the output in the form of integer, but i have problem with line
Code:
out_c <= to_integer(unsigned(count));
which doesn't change count from std_logic_vector to out which is integer.
i see these errors
Code:
(vcom-1078) Identifier "unsigned" is not directly visible.
 

Re: convert std_logic_vector to integer

unsigned is defined in both numeric_std and std_logic_arith.

At this point, std_logic_arith.all should not be used. If you want to use functions not defined in numeric_std, you should import them specifically.
 
Re: convert std_logic_vector to integer

Choose whatever conversion you have to do.

Libraries used:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


std_logic_vector to integer:

signal a : std_logic_vector (3 downto 0);
signal b : integer range 0 to 15;

b <= to_integer(unsigned(a));

--------------------------------------------

integer to std_logic_vector:

signal frm_cnt : integer range 0 to 255;
signal frm_cnt_out : std_logic_vector(7 downto 0);

frm_cnt_out <= std_logic_vector(to_unsigned(frm_cnt, 8)); -- value 8 must match to the size of frm_cnt_out

--------------------------------------------

std_logic_vector to unsigned:

signal rgmii_column : std_logic_vector(7 downto 0);
signal jf_rx_mtu : unsigned(7 downto 0);

jf_rx_mtu <= unsigned(rgmii_column);

--------------------------------------------

unsigned std_logic_vector:

signal fifo_wr_length : unsigned(10 downto 0);
signal fifo_wr_length_out : std_logic_vector(10 downto 0);

fifo_wr_length_out <= std_logic_vector(fifo_wr_length);

--------------------------------------------
 

Re: convert std_logic_vector to integer

Choose whatever conversion you have to do.

As vGoodTimes already pointed out, the error comes about because the OP used both numeric_std and std_logic_arith, that both declared an unsigned type. When this happens, unless you put in the full path to the types, the unsigned types are invisible.
 

Re: convert std_logic_vector to integer

The intention my post was to show the OP how to do the intended type conversions without the use of ieee.std_logic_unsigned.ALL and use IEEE.STD_LOGIC_ARITH.ALL libraries.
 

There is this weird obsession with numeric_std that leads to devs being very vocal about std_logic_unsigned while being much less vocal about Verilog. Basically, if you are against std_logic_unsigned you should not even acknowledge Verilog as a HDL. You should be aggressively shaming all Verilog users for the same objective reasons you are so vocal about std_logic_unsigned. There are legitimate reasons to be against Verilog/std_logic_unsigned, but they basically never enter the argument.
 

There is this weird obsession with numeric_std that leads to devs being very vocal about std_logic_unsigned while being much less vocal about Verilog. Basically, if you are against std_logic_unsigned you should not even acknowledge Verilog as a HDL. You should be aggressively shaming all Verilog users for the same objective reasons you are so vocal about std_logic_unsigned. There are legitimate reasons to be against Verilog/std_logic_unsigned, but they basically never enter the argument.

I dont think thats fair.
Verilog and VHDL had different intent. Verilog was meant to be hardware focused, and based on C, whereas VHDL was aimed at higher level modelling and based on ADA, which has strong typing. So when synopsys tried to make VHDL more like verilog they caused issues of cross platform incompatibility. This has not been a problem for a long time but std_logic_unsigned goes against the "spirit" of the language.

I would say verilog is a pretty broken language - it has features that are not backwards compatible across versions, and as you get into SV and SVA its all a mess with different syntax for the same things in different places, all because SV was a coming together of several languages.
VHDL is relatively unchanged since it's inception, which I think proves how clean it was in the first place.
People took to Verilog because they knew C. People seem to hate the strong typing in VHDL - but it can be a very powerful language when used correctly.
 

As pointed out, the error has been caused by importing two incompatible libraries. (Incompatible in the sense that you can't use the library types without explicit qualification after that).

std_logic_unsigned is not incomptable with numeric_std and can still be used after omitting STD_LOGIC_ARITH.

In so far the discussion about using or avoiding the "lazy vhdl writers" std_logic_unsigned library is slightly of topic. Personally I don't like it, but I see that VHDL2008 has essentially adopted the concept as a language option, thus I won't argue against it.

std_logic_unsigned goes against the "spirit" of the language
Yes, at least you can get on your VHDL code well or even better without it.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top