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    Interfacing a VGA port with a PLD

    Hi,

    I was planning to interface a VGA port with a Xilinx CPLD. I went across several schematics available at digilent site. In one schematic here, one I/O pin each (of FPGA) is assigned to Red, Green and Blue channels. In another schematic here 3 I/O pins are assigned to Red and Green channels and 2 I/O pins to Ble channel. Next, in yet another schematic here 4 I/O pins are assigned to Red, Green and Blue channels.

    **What could be the reason pls. ? Are multiple pins for 256 colour display? If not (I am tempted to guess otherwise as all the 3/4 pins are tied to single pin of the DB15 female connector), can I simply use one pin per channel and get the same output on VGA display instead of 2/3/4 pins per channel?

    ** Also, how were these resistance values calculated ? Is there any standard which governs the resistance value of the interfacing of the VGA port ?

    Thanking You,
    Arvind Gupta

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    Re: Interfacing a VGA port with a PLD

    Hi,

    One pin per color: Color ON/OFF
    2 pins per color: 4 steps resolution: : 0%, 33%, 66%, 100% of colour (Did you recognize the different resistor values: 2k, 1k, 510R)
    3 pins per color: 8 steps resolution: : 0%, 14% ... 100%

    Klaus


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    •   Alt25th October 2017, 08:22

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    Re: Interfacing a VGA port with a PLD

    VGA interface have one pin assigned for each colour in analog form.



    •   Alt25th October 2017, 09:19

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    Re: Interfacing a VGA port with a PLD

    OK. How were the values of the on board resistors decided here? Considering the basic configuration in which only one FPGA pin per colour channel is assigned (pdf link to schematic here), the voltage at FPGA pin can be up to 3.3 v. As per the user guide of the kit here (page 53), there is a 75 ohm termination built in the cable. If the value of the on-board resistor is R, then the equation comes out to be:

    R + 75 = (3.3-0.7) / I

    So what value of I should I take? Also if this sounds correct (which is my main motive behind this post), is there any recommended value of I (and consequently R)? Are there any VGA standards on the current to be sourced/ taken out from the VGA port?


    Similarly, how were the on board resistor values for HYSNC and VSYNC decided? Again, if it is R’, the maximum voltage at FPGA I/O pin is taken to be 3.3 v and with a 75 ohm termination built in the cable, the equation comes out to be:

    R’ + 75 = (3.3 - 0.7) / I’

    What would be the value of I’ which should be taken in this case? And again, if there are any VGA standards in this case recommending the current for these two pins pls?

    Back calculation with the given values reveal I =7.5 mA and I’= 16.5 mA (which are far apart from each other).

    In a nutshell, I wanted to understand how these values are decided and then if required, modify them in my case.

    Thanks and Regards,
    Arvind Gupta



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    Re: Interfacing a VGA port with a PLD

    No known current spec for such inputs(as far i know.)
    Since it is the monitor input that loads , that must be hi impedance with negligible current.

    for a 3.3v system RGB resistor can be calculated as around 278 ohms.
    no need for current spec.



    •   Alt25th October 2017, 13:02

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    Re: Interfacing a VGA port with a PLD

    Hi,

    nonsense.

    None of you both is able to have a look to Wikipedia? Or use an internet search engine?

    https://en.wikipedia.org/wiki/Video_Graphics_Array

    --> It specifies 75Ohms termination on both ends
    and 0.7Vpp signal level.

    So the spcification is here, but wether you keep on it is your decision.
    For a high picture quality you need to ensure 75R source impedance, but for a simple solution I´d forget about this, just rely o n the 75 Ohms in the monitor.

    ***
    if you have three 3.3V outputs and use 3 resitors then:
    all switched to 3.3V should generate 0.7V at the monitor (75 R)---then you need about 275 ohms source impedance.
    use 2k, 1k and 470R

    Klaus


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    Re: Interfacing a VGA port with a PLD

    Hi,

    Thanks for the tips. Yes, I was able to calculate the resistor when single FPGA pin is assigned to each color channel (my calculated value came out to be 279 ohms; the value of resistance in the digilent schematic was 270 ohms.). I still have a few doubts though:

    1. In the Wikipedia page, the voltage mentioned for each colour channel is 0.7 v peak to peak. Should it not be 0.7 v peak.

    2. Why did they connect 82.5 ohms in HSYNC and VHYSNC ports. I suppose 75 ohm resistors should be available easily.

    Regards,
    Arvind Gupta



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    Re: Interfacing a VGA port with a PLD

    Hi,

    1) Yes, from your point of view, because you see positive voltages only. But I assume within the monitor the signal is AC coupled --> then the definition via Vpp is more adequate. (and fits in either case)

    2) The color signals have to be seen as analog signals. But HSYNC and VSYNC are digital signals with TTL levels. About <0.7V for LOW, >2.0V for HIGH. The sync signals are NOT terminated with 75 Ohms inside the monitor. But a series resistor (82 Ohms) at the driver reduces ringing.

    Klaus



    •   Alt26th October 2017, 11:24

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    Re: Interfacing a VGA port with a PLD

    Hi there,

    I was trying to calculate the resistor values for inputs to the RGB channels with 3 bit resolution connected to the VGA port given in the digilent schematic here. I was not getting the values as per the schematic.

    For eg. the red channel has a 3 bit resolution. When Red0 will be high and other 2 inputs (Red1 and Red2) will be low, the input string for red channel will be ‘001’. In this case, the voltage at other end of the resistor should be 0.1v (assuming that 0.7v drop which is to be available at output pin of VGA is linearly divided in 8 divisions between 0.0v to 0.7 v) . So the resistance comes out to be:

    (3.3 - 0.1)/R17 = 0.1/75 (for 75 ohm termination)

    R17 = 2.4Kohms (as per the schematic it is 2.0Kohms)

    Similarly calculating for R18 (‘010’ input string and 0.2v drop at other end of the resistor), the value comes out to be 1.163Kohms. The schematic value is 1Kohms. And the calculated value for R20 is 543 ohms and whereas in the schematic it is 510 ohms.

    Can anyone point out the reason for this difference pls? Also, why has blue channel been given only 2 bit resolution against 3 bit resolution for red and green channels?

    Thanks and Regards,
    Arvind Gupta.



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    Re: Interfacing a VGA port with a PLD

    Hi,


    Can anyone point out the reason for this difference pls? Also, why has blue channel been given only 2 bit resolution against 3 bit resolution for red and green channels?
    --> https://en.wikipedia.org/wiki/8-bit_color

    Klaus
    Please don´t contact me via PM, because there is no time to response to them. Thank you.


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  11. #11
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    Re: Interfacing a VGA port with a PLD

    OK. And what could be the reason for difference in the calculated and schematic resistor values pls?

    Arvind Gupta.



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