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Core layout separation from IO pads

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saha.123

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Hi....
Why core layout is kept away(in few cases 20um) from IO pads?

Thanks
 

IO pads use to be wire bonded. This is a macroscopic-mechanical procedure with a movement inaccuracy of several microns. One doesn't really want to scratch the micro-/nanoscopic active structures nearby.
 

IO pads use to be wire bonded. This is a macroscopic-mechanical procedure with a movement inaccuracy of several microns. One doesn't really want to scratch the micro-/nanoscopic active structures nearby.
Hi Erikl,
Could you explain it detail?
If have any docs,please share

Thanks
 

Could you explain it detail?
Could you tell which detail?

Wire bonding - additionally to it's macroscopic inaccuracy compared to (sub)micron structure size - exerts a relatively high pressure locally at the pads. This pressure exerts mechanical stress on the silicon crystal, which spreads out several tens of microns (also) in the direction of the silicon core. Stress means changes of the crystal microstructure, inducing defects, which - on their part - may change electrical properties like doping concentration and charge carriers' life-time.

That's why you need corresponding spacing between the pads and the electrically working structures in the core.

I guess you can find a lot of explanations if you search for some of the above marked buzz words.
 

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