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May i please know what are "jogs" in digital or analog layouts.

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Re: may i please know what are "jogs" in digital or analog layouts.

jogs.jpg

This is what i've understood from the internet search and from what people have said.

From the above diagram, lets suppose that all three A, B, C are all M1 layers.

So what i've understood is that, A is basically a path, B is basically a polygon and C is two paths, one being vertical and the other being horizontal. Now when we observe 'C' carefully, we can see a small protruding M1, towards to right side. Is this what they call a jog. And are jogs supposed to be minimized, as in increases the number of vertex in a GDSII file.

Please provide your valuable thoughts on this.

Thanks,
Arokia

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The reason i've come up with this doubt is that I've read the below text from the book "CMOS IC Layout" by "Dan Clein" under the topic "Layout Generation Tools" and sub topic "Compactors"

Layout Generation Tools
----------------------------
Compactors
--------------

A Compactor can be used at almost all level of layout Complexity. Most of them are best used at a transistor or cell level. The tool is used to compact transistor layout and their connections inside a cell design.

One approach to using this type of tool is for the layout designer to do a loose job and run the compactor to optimize the layout. This is very fast and efficient methodology to generate DRC clean layout cells.

For cell-level layout, the setup and maintenance of a compactor requires a very knowledgeable designer. The advanced compactors that are available today, together with schematic or netlist-driven layout generators, can provide the best of all worlds because the result is correct by construction and should pass both DRC and LVS checks. In the case where the compactor works on symbolic layout data, the results are extremely fast, and they can add advanced structures such as jogs within a wire if required.

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jogs1.png

sorry for my bad drawing, i've redrawn it in paint for a clearer picture.
 
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May i please know what JOGS are in digital or analog layouts.

See the part of attached research paper "FAST ALGORITHMS FOR ONE DIMENSIONAL COMPACTION WITH JOG INSERTION" by Matthias Stallmann and Thomas Hughes (North Carolina University and IBM Corp)

Click on the PICTURE to zoom.

Capture.PNG

Also see the attached PDF.

I hope, it will answer the query.

Regards,
Maqbool
 

Attachments

  • 3-540-57155-8_282.pdf
    110.6 KB · Views: 153

jogs.png

This is what i've learned about jogs. From the above diagram, lets say we are working on a 90nm technology, and the minimum width of M1 metal layer is 0.12µm. Now the places where ever we see an edge having less than the minimum DRC (design Rule check) (ie less than 0.12µm) is considered a jog, and these jogs are to be avoided. The reason is that, its very hard to manufacture masks containing such valued edges, or during the fabrication process, the edge or that region containing the edge may not print on the wafer precisely as per the mask. So Figure A contains no jogs, but Figure B contains a jog.

Correct me if i'm wrong, please do provide your valuable thoughts.
 

I think both of these layouts / shapes are called jogs.
The second one causes "jog DRC violation", so most likely it is shortcut to just "jog".
There is a lot of (unnecessary) jargonisms / shortcuts used in technology language...
 
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