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While doing synthesis or PnR, how can I use other blocks that I created as subblock?

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kong0329

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Hello.

I am trying to do something similar to hard macro or hierarchical synthesis.

Here, I have UnitA. I finished synthesis and PnR for this UnitA block. So, I now have FRAM, netlist verilog, sdf etc. about this block UnitA.

Now I am trying to synthesize and PnR for UnitB. UnitB is composed of 4X4 (sixteen) UnitA plus other blocks and logics.
However, I just want to use the result of UnitA that I did before.
Which means, I want to use result of UnitA just like as I am using standard cells.

How I can do it?

In my opinion, I have to create .lib or .db file for UnitA and use it as link_library, but I have no idea how to create it.
Or, is there any other way that I can use FRAM just like as standard cell library?

Thanks.
 

kong0329 said:
Hello.

I am trying to do something similar to hard macro or hierarchical synthesis.

Here, I have UnitA. I finished synthesis and PnR for this UnitA block. So, I now have FRAM, netlist verilog, sdf etc. about this block UnitA.

Now I am trying to synthesize and PnR for UnitB. UnitB is composed of 4X4 (sixteen) UnitA plus other blocks and logics.
However, I just want to use the result of UnitA that I did before.
Which means, I want to use result of UnitA just like as I am using standard cells.

How I can do it?

In my opinion, I have to create .lib or .db file for UnitA and use it as link_library, but I have no idea how to create it.
Or, is there any other way that I can use FRAM just like as standard cell library?

Thanks.
Click to expand...

budgeting between partitions is a pain in the ass. you want to avoid that. just do a flat design, the industry has acknowledged that is better to let 100 machines crank at your problem instead of putting lots of engineers to put puzzles together.
 

Hierarchical synthesis is here for that if your design is so large that could not be handle in one pass.
 

rca said:
Hierarchical synthesis is here for that if your design is so large that could not be handle in one pass.
Click to expand...

my point is that hierarchical synthesis works, but industry is no longer keen on using it. make it flat whenever possible.
 

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