Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Find out the area of sub-modules of a Verilog design using Synopsys design compiler

Status
Not open for further replies.
M

mahbod72

Newbie level 1
Joined
Aug 26, 2017
Messages
0
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
0
Hi friends,

I want to know how can I find out the area of sub-modules of a Verilog design using Synopsys design compiler.

Please let me know if you have any questions.
 

report_read -hierarchy
With the depth you could have your sub-modules
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top